
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-5
PCI PCB DESIGN LAYOUT GUIDELINES
Careful attention must always be exercised when be-
ginning the design and layout phase of any new
printed circuit board. It is only through careful plan-
ning and the usage of good electrical design prac-
tices that long term product reliability may be
achieved. Careful attention to layout issues of EMI,
cross-talk and decoupling will avoid engineering pro-
totype development problems and future production
failures due to an "on the edge" design.
Designs incorporating PCI devices have specific
printed circuit board layout requirements in order to
comply with industry standard PCI local bus specifi-
cations. In addition to these requirements, AMCC's
S5933 PCI controller has specific requirements to
ensure proper function and long life. This applica-
tions note is supplied by AMCC as factory recom-
mended PCB design layout guidelines for printed
circuit boards incorporating the S5933 PCI control-
ler. The following sections detail important design
areas concerning PCB design, power decoupling,
ferrite beads and critical trace layout.
PCB DESIGN
AMCC highly recommends the use of a four layer
printed circuit board. This is due to the expected
high trace density in most PCI designs incorporating
PLCC and PQFP devices. Four layer designs signifi-
cantly overcome ground noise problems associated
with most two layer PCBs. Should a two layer design
be implemented, leave as much copper on the PCB
as possible for all power distribution traces. This is
extremely important in ground traces to avoid ground
loops and ground potential problems. Also utilize
multiple feed-thrus for large traces. A 100 mil trace
with a single 0.030 feed thru has it's current carrying
capability significantly reduced.
DECOUPLING
The AMCC PCI controller is an application specific
standard product (ASSP) utilizing CMOS technology.
Although CMOS technology is commonly known for
it's noise immunity properties, special consideration
must still be given to electrical noise generated due
to the high speed signals utilized in a PCI design.
The first design issue of concern is decoupling. By
"decoupling", the designer provides a means to dis-
sociate circuit functions from the power bus serving
that circuit. This "means" is provided through the us-
age of decoupling capacitors, ferrite beads and
proper printed circuit board trace layout. The lack of
correct decoupling increases both radiated and con-
ducted emissions which increases electrical noise
and susceptibility to circuit failure (i.e. erratic and
intermittent circuit functions or "FLAKYNESS").
To reduce these problems, AMCC recommends PCI
designs incorporate a low speed PCB decoupling ca-
pacitor. Select a 10uF (minimum) tantalum or metal-
ized polycarbonate (not aluminum) capacitor for this
purpose. Specify a low ESR type at a working volt-
age slightly above the circuit's operating voltage. Lo-
cate the capacitor no more than 300 mils from the
PCB's power entry point as shown in figure 1. This
point is likely the PCB edge fingers or a wire connec-
tor interfacing the PCB to the system power supply.
AMCC also recommends the use of one high speed
0.1uF decoupling capacitor per PCB IC package.
Specify an X7R or BX type dielectric ceramic chip
capacitor also rated slightly above required working
voltage for this purpose. Locate each capacitor next
to and on the same side of the PCB as each IC
device. Locate capacitors no more than 150 mils
from each IC package's ground pin. High speed
decoupling for the S5933 PCI controller IC requires
one 0.1uF per power and ground pin pair. IMPOR-
TANT: Locate these capacitors on the same side of
the PCB as the S5933 at a distance of less than 150
mils as shown in Figure 1.
The use of the above capacitors will sufficiently
decouple the Vcc and ground planes from high and
low speed circuit functions. One last decoupling is-
sue of concern involves any unused PCI edge con-
nector power fingers. Industry PCI specifications
provides for power sources of +3.3V and +5V within
the PCI edge connector. PCI specifications require
any unused power and V I/O pins on the PCI edge
connector be decoupled to the ground plane with an
average of 0.01uF.
APPLICATION NOTE