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參數(shù)資料
| 型號： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 53/327頁 |
| 文件大小： | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
10-5
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
If the S5933 is programmed to generate a PCI inter-
rupt (INTA#), on an Add-On write to outgoing mailbox
4, byte 3, a rising edge on EMBCLK generates a PCI
interrupt. The bits EMB7:0 can be read by the PCI
bus interface by reading the PCI incoming mailbox 4,
byte 3. These bits are useful to indicate various con-
ditions which may have caused the interrupt.
When using the S5933 with a byte-wide boot device,
the capability to generate PCI interrupts with Add-On
hardware does not exist. In this configuration, PCI
incoming mailbox 4, byte 3 (Add-On incoming mail-
box 4, byte 3) cannot be used to transfer data from
the Add-On - it always returns zeros when read from
the PCI bus. This mailbox byte is sacrificed to allow
the added functionality provided when a byte-wide
boot device is not used.
10.2 BUS INTERFACE
The mailboxes appear on the Add-On and PCI bus
interfaces as eight operation registers. Four are out-
going mailboxes, four are incoming mailboxes. The
mailboxes may be used to generate interrupts to
each of the interfaces. The following sections de-
scribe the Add-On and PCI bus interfaces for the
mailbox registers.
10.2.1 PCI Bus Interface
The mailboxes are only accessible with the S5933 as
a PCI target. The mailbox operation registers do not
support burst accesses by an initiator. A PCI initiator
attempting to burst to the mailbox registers causes the
S5933 to respond with a target disconnect with data
(Section 8.1.5.1.). PCI writes to full outgoing mail-
boxes overwrite data currently in that the mailbox. PCI
reads from empty incoming mailboxes return the data
that was previously contained in the mailbox. Neither
of these situations cause a target retry or abort.
PCI incoming and outgoing mailbox interrupts are en-
abled in the Interrupt Control/Status Register
(INTCSR). The mailboxes can generate a PCI inter-
rupt (INTA#) under two conditions (individually en-
abled). For an incoming mailbox full interrupt, INTA#
is asserted on the PCI clock rising edge after the
Add-On mailbox write completes. For an outgoing
mailbox empty interrupt, INTA# is asserted on the
PCI clock rising edge after the Add-On mailbox read
completes (the rising edge of RD#). INTA# is
deasserted on the next PCI clock rising edge after
the PCI access to clear the mailbox interrupt com-
pletes (TRDY# deasserted).
10.2.2 Add-On Bus Interface
The Add-On mailbox interface behaves similar to the
PCI bus interface. Add-On writes to full outgoing
mailboxes overwrite data currently in that mailbox.
PCI reads from empty incoming mailboxes return the
data that was previously contained in the mailbox.
Add-On incoming and outgoing mailbox interrupts are
enabled in the Add-On Interrupt Control/Status Reg-
ister (AINT). The mailboxes can generate the Add-On
IRQ# interrupt under two conditions (individually en-
abled). For an incoming mailbox full interrupt, IRQ# is
asserted one PCI clock period after the PCI mailbox
write completes (TRDY# deasserted). For an outgo-
ing mailbox empty interrupt, IRQ# is asserted one
PCI clock period after the PCI mailbox read com-
pletes (TRDY# deasserted). IRQ# is deasserted im-
mediately when the Add-On clears the mailbox
interrupt (see Chapter 13 for exact timing).
When the S5933 is used with a serial nv memory boot
device or no external boot device, the device pins
EA8:0 are redefined as shown in Section 10.1.3.
EA7:0 become EMB7:0 data inputs and EA8 becomes
EMBCLK, a load clock. This configuration allows the
Add-On to generate PCI interrupts with a low-to-high
transition on EMBCLK. The PCI incoming mailbox in-
terrupt must be enabled and set for mailbox 4, byte3 in
the PCI Interrupt Control/Status Register (INTCSR).
EMBCLK should begin high and be pulsed low, then
high to be recognized (see Chapter 13 for exact tim-
ing). The rising edge of EMBCLK generates the inter-
rupt. The rising edge of EMBCLK also latches in the
values on EMB7:0. The S5933 interrupt logic must be
cleared (INTA# deasserted) through INTCSR before
further EMBCLK interrupts are recognized.
10.2.2.1 8-Bit and 16-Bit Add-On Interfaces
Some Add-On designs may implement an 8-bit or 16-
bit bus interface. The mailboxes do not require a 32-
bit Add-On interface. For 8-bit interfaces, the 8-bit
data bus may be externally connected to all four
bytes of the 32-bit Add-On interface (DQ 31:24,
23:16, 15:8, 7:0 are all connected). The Add-On de-
vice reading or writing the mailbox registers may ac-
cess all mailbox bytes by cycling through the Add-On
byte enable inputs. A similar solution applies to 16-bit
Add-On buses. This solution works for Add-Ons
which always use just 8-bit or just 16-bit accesses.
If the MODE pin is high, indicating a 16-bit Add-On
interface, the previous solution may be modified for an
8-bit interface. The difference is that ADR1 must be
toggled after the first two accesses to steer the S5933
internal data bus to the upper 16-bits of the mailboxes.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S5933QC | 制造商:AMC 功能描述:IC |
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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