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參數(shù)資料
| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 38/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
9-3
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
9.0
ADD-ON BUS INTERFACE
This chapter describes the Add-On bus interface for
the S5933. The S5933 is designed to support con-
nection to a variety of microprocessor buses and/or
peripheral devices. The Add-On interface controls
S5933 operation through the Add-On Operation Reg-
isters. These registers act as the Pass-Thru, FIFO,
non-volatile memory and mailbox interfaces as well
as offering control and status information.
Depending on the register being accessed, the inter-
face may be synchronous, asynchronous, or
configurable. To enhance performance and simplify
Add-On logic design, some registers allow direct ac-
cess with a single device input pin. The following
sections describe the various interfaces to the PCI
bus and how they are accessed from the Add-On
interface.
9.1
ADD-ON OPERATION REGISTER
ACCESSES
The S5933 Add-On bus interface is very similar to
that of a memory or peripheral device found in a
microprocessor-based system. A 32-bit data bus with
individual read and write strobes, a chip enable and
byte enables are provided. Other Add-On interface
signals are provided to simplify Add-On logic design.
Accesses to the S5933 registers are done synchro-
nous or asynchronous to BPCLK. For S5933 functions
that are compatible with an Add-On microprocessor
interface, it is helpful to allow an asynchronous inter-
face, as the processor may not operate at the PCI bus
clock frequency.
9.1.1 Add-On Interface Signals
The Add-On interface provides a small number of
system signals to allow the Add-On to monitor PCI
bus activity, indicate status conditions (interrupts),
and allow Add-On bus configuration. A standard bus
interface is provided for Add-On Operation Register
accesses.
9.1.1.1 System Signals
BPCLK and SYSRST# allow the Add-On interface to
monitor the PCI bus status. BPCLK is a buffered ver-
sion of the PCI clock. The PCI clock can operate
from 0 MHz to 33 MHz. SYSRST# is a buffered ver-
sion of the PCI reset signal, and may also be toggled
by host application software through bit 24 of the Bus
Master Control/Status Register (MCSR).
IRQ# is the Add-On interrupt output. This signal is
active low and can indicate a number of conditions.
Add-On interrupts may be generated from the mail-
box or FIFO interfaces. The exact conditions which
generate an interrupt are discussed in the mailbox
and FIFO chapters. The interrupt output is
deasserted when acknowledged by an access to the
Add-On Interrupt Control/Status Register (AINT). All
interrupt sources are cleared by writing a one to the
corresponding interrupt bit.
The MODE input on the Add-On interface configures
the datapath width for the Add-On interface. MODE
low indicates a 32-bit data bus. MODE high indicates
a 16-bit data bus. For 16-bit operation, BE3# is rede-
fined as ADR1, providing an extra address input.
ADR1 selects the low or high words of the 32-bit
S5933 Add-On Operation Registers.
9.1.1.2 Register Access Signals
Simple register accesses to the S5933 Add-On Op-
eration Registers take two forms: synchronous to
BPCLK and asynchronous. The following signals are
required to complete a register access to the S5933.
BE[3:0]# Byte Enable Inputs. These S5933 inputs
identify valid byte lanes during Add-On transac-
tions. When MODE is set for 16-bit operation,
BE2# is not defined and BE3# becomes ADR1.
ADR[6:2] Address Inputs. These address pins iden-
tify the specific Add-On Operation Register being
accessed. When configured for 16-bit operation
(MODE=1), an additional input, ADR1 is avail-
able to allow the 32-bit operation registers to be
accessed with two 16-bit cycles.
RD# Read Strobe Input.
WR# Write Strobe Input.
SELECT# Chip Select Input. This input identifies a
valid S5933 access.
DQ[31:0] Bidirectional Data Bus. These I/O pins are
the S5933 data bus. When configured for 16-bit
operation, only DQ[15:0] are valid.
In addition, there are dedicated signals for FIFO ac-
cesses (RDFIFO# and WRFIFO#) and Pass-Thru ad-
dress accesses (PTADR#). These are discussed
separately in the FIFO and Pass-Thru sections of this
chapter.
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