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參數(shù)資料
| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 21/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
8-4
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
8.1.1 PCI Burst Transfers
The PCI bus, by default, expects burst transfers to be
executed. To successfully perform a burst transfer,
both the initiator and target must order their burst
address sequence in an identical fashion. There are
two different ordering schemes: linear address
incrementing and 80486 cache line fill sequencing.
The exact ordering scheme for a bus transaction is
defined by the state of the two least significant AD
lines during the address phase. The decoding for
these lines is shown below:
AD[1:0]
Burst Order
0 0
Linear sequence
0 1
Reserved
1 0
Cacheline Wrap Mode
1 1
Reserved
The S5933 supports both the linear and the cache
line burst ordering. When the S5933 controller is an
initiator, it always employs a linear ordering.
Some accesses to the S5933 controller (as a target)
can not be burst transfers. For example, the S5933
does not allow burst transfers when accesses are
made to the configuration or operation registers (in-
cluding the FIFO as a target). Attempts to perform
burst transfers to these regions cause STOP# to be
asserted during the first data phase. The S5933 com-
pletes the initial data phase successfully, but assert-
ing STOP# indicates that the next access needs to
be a completely new cycle. Accesses to memory or I/
O regions defined by the Base Address Registers 1-4
(see Section 4.11) may be bursts, if desired.
8.1.2 PCI Read Transfers
The S5933 responds to PCI bus memory or I/O read
transfers when it is selected (target). As a PCI bus
initiator, the S5933 controller may also produce PCI
bus memory read operations.
Figure 8-1 depicts the fastest burst read transfer pos-
sible for the PCI bus. The timings shown in Figure 8-
1 are representative of the S5933 as a PCI initiator
with a fast, zero-wait-state memory target. The sig-
nals driven by the S5933 during the transfer are
FRAME#, C/BE[3:0]#, and IRDY#. The signals driven
by the target are DEVSEL# and TRDY#. AD[31:0]
are driven by both the target and initiator during read
transactions (only one during any given clock). Clock
period 2 is a required bus turn-around clock which
ensures bus contention between the initiator and tar-
get does not occur.
Targets drive DEVSEL# and TRDY# after the end of
the address phase (boundary of clock periods 1 and
2 of Figure 8-1). TRDY# is not driven until the target
can provide valid data for the PCI read. When the
S5933 becomes the PCI initiator, it attempts to per-
form sustained zero-wait state burst reads until one
of the following occurs:
The memory target aborts the transfer
PCI bus grant (GNT#) is removed
The PCI to Add-On FIFO becomes full
A higher priority (Add-On to PCI) S5933
transfer is pending (if programmed for priority)
The read transfer byte count reaches zero
Bus mastering is disabled from the Add-On
interface
Figure 8-1. Zero Wait State Burst Read PCI Bus Transfer (S5933 as Initiator)
12
3
45
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
TRDY#
DEVSEL#
ADDRESS
DATA (2)
DATA (3)
(T)
DATA (1)
BYTE EN (2)
BYTE EN (3)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
BYTE ENABLES (1)
BUS COMMAND
(I)
(T)
(I)
(T)
6
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