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參數(shù)資料
| 型號： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 159/327頁 |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-14
BUS MASTERING WITH THE S5933 PCI MATCHMAKER
Each application’s interrupt handler must first check
the source of the interrupt. For S5933 applications,
this is done by reading the S5933 Interrupt Control/
Status Register. The status of all possible S5933
PCI interrupt sources is indicated by this register. If
the status bits indicate that no interrupts were gener-
ated by the S5933, the handler must call the previ-
ous interrupt handler whose vector it replaced. The
previous interrupt handler then performs a similar
task for the device it services, and this process con-
tinues until the device which generated the interrupt
is found.
If the interrupt handler determines that the source of
the interrupt was the S5933, the interrupt source
must be cleared through the Interrupt Control/Status
Register (INTCSR). The handler then performs what-
ever tasks are necessary to service the interrupt
(such as rewriting address or transfer count regis-
ters). Finally, the handler must clear the 83C59A in-
terrupt controller ‘in-service’ bit. This bit is set when
the host processor acknowledges the interrupt and
jumps to the interrupt service routine. A specific end-
of-interrupt (EOI) is used to clear this bit. If a PCI
device is mapped to hardware interrupts IRQ8 to
IRQ15, two EOI commands must be issued. One
EOI must be issued for the slave 82C59A which sup-
ports IRQ8-15. A second EOI is required for the
master 82C59A. The second EOI is a specific EOI
for IRQ2 because the slave interrupt controller in a
PC is cascaded into the IRQ2 input of the master
interrupt controller. Without the end-of-interrupt se-
quence, the interrupt controllers will not recognize
further interrupts from that source.
4.0 PCI DMA PERFORMANCE FACTORS
There are a number of factors which determine DMA
performance on the PCI bus. The clock speed and
data bus width are important in determining maxi-
mum bus bandwidth. The most important factor in
DMA performance is traffic on the PCI bus. As the
number of PCI devices which require access to the
bus increases, the bandwidth available to each indi-
vidual device decreases.
4.1
PCI Bus Arbitration
Each device on the PCI bus has a dedicated REQ#/
GNT# pair which are connected to the system bus
arbiter. When a device asserts REQ#, it indicates a
data transfer is required. The transfer may be a
single data phase or a burst. The bus arbiter asserts
GNT# to the device to indicate that it may now per-
form the transfer.
The bus arbiter may remove GNT# from a PCI bus
master on any PCI clock. The current transaction
completes, and the PCI master gives up control of
the bus. GNT# may already be asserted to the next
master, but it is not allowed to drive the PCI bus until
IRDY# and FRAME# are deasserted, indicating the
bus is idle. If the original bus master has more data
to be transferred, it may keep REQ# asserted, but
must wait for GNT# again.
The priority scheme used to determine which PCI
device controls the bus at a given time is determined
by the system. The PCI specification requires a few
extra Configuration Registers within PCI bus master
devices. During system initialization, these registers
are read to determine each device’s requirements (if
any). Based on these, a priority scheme can be de-
fined which is unique to that system. Ideally, the ar-
bitration scheme gives priority to devices with higher
bandwidth requirements, but does not prevent other
PCI bus masters from gaining control of the bus.
4.2
PCI Bus Access Latency
There are three components to latency on the PCI
bus. The total latency is measured from the time a
bus master requests the bus (asserts REQ#) to
when the target of the transfer completes the trans-
fer (asserts TRDY#). Each of these components is
described in the following sections.
4.2.1
Arbitration Latency
Once a PCI device asserts REQ#, it must wait for
the bus arbiter to assert GNT#. This delay is called
arbitration latency. This is determined by the priority
scheme used by the bus arbiter, the relative priority
of the device requesting the bus, and the amount of
activity on the PCI bus.
4.2.2
Bus Acquisition Latency
Once a PCI device receives GNT# from the arbiter, it
must wait for the current bus master to complete it’s
transaction (indicated by FRAME# and IRDY#
deasserted) before driving the PCI bus. Bus acquisi-
tion latency is the time from when GNT# is received to
when FRAME# is asserted by a particular master.
This is determined by the length of the current bus
master’s transfer.
4.2.3
Target Latency
After a PCI device begins a bus cycle, it must wait
for the target of the transfer to complete the cycle
(by asserting TRDY#). Target latency is the time
from when FRAME# is asserted to when TRDY# is
asserted. This is unique for each target and depends
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5933QC | 制造商:AMC 功能描述:IC |
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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