
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
8-2
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
8.
PCI BUS INTERFACE ..................................................................................................... 8-3
8.1 PCI BUS TRANSACTIONS .................................................................................................................. 8-3
8.1.1 PCI Burst Transfers ................................................................................................................... 8-4
8.1.2 PCI Read Transfers ................................................................................................................... 8-4
8.1.3 PCI Write Transfers ................................................................................................................... 8-6
8.1.4 Master-Initiated Termination ...................................................................................................... 8-7
8.1.4.1
Normal Cycle Completion .......................................................................................... 8-7
8.1.4.2
Initiator Preemption ................................................................................................... 8-8
8.1.4.3
Master Abort .............................................................................................................. 8-9
8.1.5 Target-Initiated Termination ....................................................................................................... 8-9
8.1.5.1
Target Disconnects .................................................................................................. 8-10
8.1.5.2
Target Requested Retries ......................................................................................... 8-11
8.1.5.3
Target Aborts ............................................................................................................ 8-11
8.2 PCI BUS MASTERSHIP ..................................................................................................................... 8-13
8.2.1 Bus Mastership Latency Components ..................................................................................... 8-13
8.2.1.1
Bus Arbitration ......................................................................................................... 8-13
8.2.1.2
Bus Acquisition ........................................................................................................ 8-14
8.2.1.3
Target Latency ......................................................................................................... 8-14
8.2.2 Target Locking ......................................................................................................................... 8-14
8.3 PCI BUS INTERRUPTS ...................................................................................................................... 8-16
8.4 PCI BUS PARITY ERRORS ............................................................................................................... 8-16
CONTENTS