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參數資料
| 型號： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 20/327頁 |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
8-3
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
8.0
PCI BUS INTERFACE
This section describes the various events which oc-
cur on the S5933 PCI bus interface. Since the S5933
controller functions as both a target (slave) and an
initiator (master), signal timing detail is given for both
situations. Section 8.1 presents the signal relation-
ships involved in performing basic read or write trans-
fers on the PCI bus. Section 8.1 also describes the
different ways these cycles may complete. In Section
8.2 the events associated with acquiring control of the
PCI bus and becoming a PCI bus initiator (master) are
detailed. PCI Interrupts are described in Section 8.3.
8.1
PCI BUS TRANSACTIONS
Because the PCI bus has multiplexed address/data
pins, AD[31:0], each PCI bus transaction consists of
two phases: Address and Data. An address phase is
defined by the clock period when the signal FRAME#
transitions from inactive (high) to active (low). During
the address phase, a bus command is also driven by
the initiator on signal pins C/BE[3:0]#. If the command
indicates a PCI read, the clock cycle following the ad-
dress phase is used to perform a “bus turn-around”
cycle. A turn-around cycle is a clock period in which the
AD bus is not driven by the initiator or the target device.
This is used to avoid PCI bus contention. For a write
command, a turn-around cycle is not needed, and the bus
goes directly from the address phase to the data phase.
All PCI bus transactions consist of an address phase
(described above), followed by one or more data
phases. The address phase is only one PCI clock long
and the bus cycle information (address and command)
is latched internally by the S5933. The number of data
phases depends on how many data transfers are de-
sired or are possible with a given initiator-target pair. A
data phase consists of at least one PCI clock. FRAME#
is deasserted to indicate that the final data phase of a
PCI cycle is occurring. Wait states may be added to any
data phase (each wait state is one PCI clock).
The PCI bus command presented on the C/BE[3:0]#
pins during the address phase can represent 16 pos-
sible states. Table 8-1 lists the PCI commands and
identifies those which are supported by the S5933 con-
troller as a target and those which may be produced by
the S5933 controller as an initiator. A “Yes” in the “Sup-
ported As Target” column in Table 8-1 indicates the
S5933 controller asserts the signal DEVSEL# when that
command is issued along with the appropriate PCI ad-
dress (see Sections 4.11 and 7.4). Two commands are
supported by the S5933 controller as an initiator:
Memory Read and Memory Write.
The completion or termination of a PCI cycle can be
signaled in several ways. In most cases, the comple-
tion of the final data phase is indicated by the asser-
tion of ready signals from both the target (TRDY#)
and initiator (IRDY#) while FRAME# is inactive. In
some cases, the target is not be able to continue or
support a burst transfer and asserts the STOP# sig-
nal. This is referred to as a target disconnect. There
are also cases where an addressed device does not
exist, and the signal DEVSEL# never becomes ac-
tive. When no DEVSEL# is asserted in response to a
PCI cycle, the initiator is responsible for ending the
cycle. This is referred to as a master abort. The bus
is returned to the idle phase when both FRAME# and
IRDY# are deasserted.
Table 8-1. Supported PCI Bus Commands
Supported
C/BE[3:0]#
Command Type
As Target
As Initiator
0000
Interrupt Acknowledge
No
0001
Special Cycle
No
0010
I/O Read
Yes
No
0011
I/O Write
Yes
No
0100
Reserved
No
0101
Reserved
No
0110
Memory Read
Yes
0111
Memory Write
Yes
1000
Reserved
No
1001
Reserved
No
1010
Configuration Read
Yes
No
1011
Configuration Write
Yes
No
1100
Memory Read Multiple
Yes 1
No 3
1101
Reserved
No
1110
Memory Read Line
Yes 1
No
1111
Memory Write & Invalidate
Yes 2
No
Notes 1: Memory Read Multiple and Read Line are treated as Memory Reads.
2: Memory Write & Invalidate commands are treated as Memory Writes.
3: Must be enabled by bit 15 MCSR.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| S5933QC | 制造商:AMC 功能描述:IC |
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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