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參數(shù)資料
| 型號： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 66/327頁 |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
11-7
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
For bus master transfers initiated by the Add-On in-
terface, some applications may not know the size of
the data block to be transferred. To avoid constantly
updating the transfer count register, the transfer
count may be disabled. Bit 28 in the Add-On General
Control/Status Register (AGCSTS) performs this
function. Disabling the transfer count also disables
the interrupt capabilities. Regardless of whether Add-
On transfer count is enabled or disabled, the Add-On
Master Read Enable (AMREN) and Add-On Master
Write Enable (AMWEN) inputs control when the
S5933 asserts or deasserts its request to the PCI
bus. When Add-On transfer count is enabled, the
S5933 will only request the bus when both the trans-
fer count (read or write) is not zero and the appropri-
ate enable line (AMREN or AMWEN) is active. For
Add-On initiated bus mastering, AMWEN and
AMREN override the read and write bus mastering
enable bits in the Bus Master Control/Status Register
(MCSR).
11.1.4.2 PCI Initiated Bus Mastering
If bit 7 in location 45h of the external non-volatile
memory is one, the Master Read Address Register
(MRAR), Master Write Address Register (MWAR), Mas-
ter Read Transfer Count (MRTC), and Master Write
Transfer Count (MWTC) are accessible only from the
PCI bus interface. In this configuration, the S5933
transfers data until the transfer count reaches zero. The
transfer count cannot be disabled for PCI initiated bus
mastering. If no external nv memory boot device is
used, the S5933 defaults to PCI initiated bus mastering.
11.1.4.3 Address and Transfer Count Registers
The S5933 has two sets of registers used for bus
master transfers. There are two operation registers
for bus master read operations and two operation
registers for bus master write operations. One opera-
tion register is for the transfer address (MWAR and
MRAR). The other operation register is for the trans-
fer byte count (MWTC and MRTC).
The address registers are written with the first ad-
dress of the transfer before bus mastering is enabled.
Once a transfer begins, this register is automatically
updated to reflect the address of the current transfer.
If a PCI target disconnects from an S5933 initiated
cycle, the transfer is retried starting from the current
address in the register. If bus grant (GNT#) is re-
moved or bus mastering is disabled (using AMREN
or AMWEN), the value in the address register reflects
the next address to be accessed. Transfers must be-
gin on DWORD boundaries.
The transfer count registers contain the number of
bytes to be transferred. The transfer count may be
written before or after bus mastering is enabled. If
bus mastering is enabled, no transfer occurs until the
transfer count is programmed with a non-zero value.
Once a transfer begins, this register is automatically
updated to reflect the number of bytes remaining to
be transferred. If the transfer count registers are dis-
abled (for Add-On initiated bus mastering), transfers
begin as soon as bus mastering is enabled.
Although transfers must begin on DWORD bound-
aries, transfer counts do not have to be multiples of
four bytes. For example, if the write transfer count
(MWTC) register is programmed with a value of 10
(decimal), the S5933 performs two DWORD writes
and a third write with only BE0# and BE1# asserted.
11.1.4.4 Bus Mastering FIFO Management
Schemes
The S5933 provides flexibility in how the FIFO is man-
aged for bus mastering. The FIFO management
scheme determines when the S5933 requests the bus
to initiate PCI bus cycles. The management scheme is
configurable for the PCI to Add-On and Add-On to PCI
FIFO (and may be different for each). Bus mastering
must be enabled for the management scheme to apply
(via the enable bits or AMREN/AMWEN).
For the PCI to Add-On FIFO, there are two manage-
ment options. The PCI to Add-On FIFO management
option is programmed through the Bus Master Con-
trol/Status Register (MCSR). The FIFO can be pro-
grammed to request the bus when any DWORD
location is empty or only when four or more locations
are empty. After the S5933 is granted control of the
PCI bus, the management scheme does not apply.
The device continues to read as long as there is an
open FIFO location. When the PCI to Add-On FIFO is
full or bus mastering is disabled, the PCI bus request
is removed by the S5933.
For the Add-On to PCI FIFO, there are two manage-
ment options. The Add-On to PCI FIFO management
option is programmed through the Bus Master Con-
trol/Status Register (MCSR). The FIFO can be pro-
grammed to request the bus when any DWORD
location is full or only when four or more locations are
full. After the S5933 is granted control of the PCI bus,
the management scheme does not apply. The device
continues to write as long as there is data in the
FIFO. When the Add-On to PCI FIFO is empty or bus
mastering is disabled, the PCI bus request is re-
moved by the S5933.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S5933QC | 制造商:AMC 功能描述:IC |
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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