
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-62
S5933
PCI CONTROLLER
Setting up a bus master transfer includes determining
the physical address at which the data transfer is to
take place. To determine a physical address from a
real-mode segment and offset, simply shift-left the
segment by 4 bits and add to the offset. This will
produce a 20-bit address. To access memory above
the 1-megabyte real-mode addressing limit, a physi-
cal address also must be determined. This is entirely
dependent upon the DOS Extender utilized and is not
addressed here.
Code Segment 7 demonstrates how to set up a Bus-
Master write and poll the PCI device to determine
when the transfer is complete.
First, the Master Write Address Register and Master
Write Transfer Count Register must be set to the
physical address of the data and the number of
BYTES to be transferred respectively. The address
must be a DWORD boundary. The transfer count is
always the number of bytes to be transferred, and
does not have to be whole multiples of a DWORD (0,
1, 2, 3, 4, ... are all legal).
Next, the transfer is started by setting the
WRITE_TRANSFER_ENABLE bit in the Bus-Master
Control-Status Register. The WRITE_TRANSFER_
COMPLETE bit in the Interrupt Control Status Regis-
ter is then polled until set. Upon completion of the
transfer, the interrupt must be cleared by writing a
one to the WRITE_TRANSFER_COMPLETE bit.
The transfer does not have to be polled until com-
plete. The transfer completion may generate an inter-
rupt if set up in the Interrupt Control Status Register
— Interrupt on Write Complete bit.
There are a few things to keep in mind with regard to
Bus-Master transfers. First, if you desire to start both
a read and a write bus-master transfer concurrently,
make sure the write to the Read/Write Transfer En-
able first examines the other bit (Write/Read Transfer
Enable respectively) to see if the transfer is still ex-
ecuting. If so, you must set both bits, or the writing of
the bit to start the transfer may stop the other transfer
from executing. Second, a FIFO transfer of the same
type (Read/Write) may not be executed at the same
time as a Bus-Master transfer, because both FIFO
and Bus-Master transfers utilize the same FIFO.
There are several parameters that may be set to
“tune” the Bus-Master transfer. These parameters
are located in the Bus Master Control Status Register
and are described in the S5933 PCI Controller Hard-
ware Specification Manual, and will not be repeated
here.
Non-Volatile Memory Access
The on-board non-volatile memory device (EEPROM
or nvRAM) on the PCI device with an S5933 PCI
Controller may be accessed from the host computer.
The Bus Master Control-Status Register is used to
access the non-volatile memory. The access makes
#define READ_TRANSFER_ENABLE
0x00004000
#define WRITE_TRANSFER_COMPLETE 0x00040000
#define READ_TRANSFER_COMPLETE 0x00080000
/* Set write from address */
outpd(amcc_op_reg_base_address + AMCC_OP_REG_MWAR,
((dword) (FP_SEG(write_data) << 4)) + FP_OFF(write_data));
/* Set transfer count */
outpd(amcc_op_reg_base_address + AMCC_OP_REG_MWTC, sizeof(write_data));
/* Enable write transfer in MCSR */
outpd(amcc_op_reg_base_address + AMCC_OP_REG_MCSR, WRITE_TRANSFER_ENABLE);
/* Wait until write transfer is complete */
while ((inpd(amcc_op_reg_base_address + AMCC_OP_REG_INTCSR)
& WRITE_TRANSFER_COMPLETE) == 0) {
/* Do nothing */
}
/* Clear Interrupt */
outpd(amcc_op_reg_base_address + AMCC_OP_REG_INTCSR, WRITE_TRANSFER_COMPLETE);
Code Segment 7