
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-38
ADD-ON DMA CONTROLLER DESIGN FOR THE S5933
The DMA controller MASTER state machine is modified slightly. The MASTER 1 state changes to prevent the
controller from starting an add-on DMA transfer while a pass-thru access to one of its registers is occurring. The
SLAVE machine requires more modification. SLAVE 0 only monitors PTATN#. If PTATN# is asserted and a
DMA transfer is not in progress, the state machine advances to SLAVE 1.
During SLAVE 1, PTADR# is
asserted and the pass-thru address is decoded, determining if the DMA address or transfer count is to be written
(or if the pass-thru access is not intended for the DMA controller). SLAVE 2 and SLAVE 3 program the
appropriate DMA registers, asserting RD# and PTRDY#. The state machine then advances to SLAVE 0, return-
ing the machine to its idle state.
The following PLD equation modifications are required to implement this function:
/* Inputs */
Pin
=
nPTATN;
/* Pass-thru Access Indicator */
Pin
=
PTNUM0;
/* Pass-thru Region Decode */
Pin
=
PTNUM1;
/* Remove HLDA Output */
/* Outputs */
Pin
=
nPTADR;
/* Pass-thru Address Strobe */
Pin
=
nRD;
/* S5933 RD# Input */
Pin
=
nPTRDY;
/* Pass-thru Access Complete Indicator */
/* ADR6:2 are hardwired to the PTDATA address */
/* HOLD output is no longer required */
/* nRDY_OUT becomes nPTRDY */
/* SELECT# and BE3:0# on the S5933 may be tied low */
/* Declarations and Intermediate Variable Definitions */
/* Remove all equations for HOLD, HLDA, nRDY_OUT */
BE3.OE
= ‘b’1;
/* DMA controller is only add-on bus master */
BE2.OE
= ‘b’1;
BE1.OE
= ‘b’1;
BE0.OE
= ‘b’1;
nPTRDY.OE = ‘b’1;
nADS.OE
= ‘b’1;
W_nR.OE
= ‘b’1;
/* Logic Equations */
/* The bus add-on bus master state machine and the add-on slave */
/* state machine change to support pass-thru programming (pt-writes) and */
/* no add-on processor */
/* Remove all equations for HOLD, HLDA, nRDY_OUT */
nPTADR = !SLAVE1;
nRD = !(SLAVE2 # SLAVE3);
nPTRDY = !(SLAVE2 # SLAVE3);