
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
8-7
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
8.1.4 Master-Initiated Termination
Occasionally, a PCI transfer must be terminated by
the initiator. Typically, the initiator terminates a trans-
fer upon the successful completion of the transfer.
These normal completions are described in Section
8.1.4.1. Sometimes, the initiator’s bus mastership is
relinquished by the bus arbiter (GNT# is removed),
often because another device requires bus owner-
ship. This is called initiator preemption and is dis-
cussed in Section 8.1.4.2. When the S5933 is an
initiator and does not observe a DEVSEL# response
to its assertion of FRAME#, it terminates the cycle
(master abort), as described in Section 8.1.4.3.
8.1.4.1 Normal Cycle Completion
A successful data transfer occurs when both the ini-
tiator and target assert their respective ready signals,
IRDY# and TRDY#. The last data phase is indicated
by the initiator when FRAME# is deasserted during a
data transfer. A normal cycle completion occurred if
the target does not assert STOP#. Figure 8-6 shows
the signal relationships defining a normal transfer
completion.
Figure 8-6. Master-Initiated, Normal Completion (S5933 as either Target or Initiator)
Figure 8-5. Single Data Phase PCI Bus Write of S5933 Registers (S5933 as Target)
PCI CLOCK
FRAME #
IRDY#
TRDY#
DEVSEL#
1
2
3
(T)
(I)
(T)
NORMAL
COMPLETION
(I)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
STOP#
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
TRDY#
DEVSEL#
STOP#
ADDRESS
DATA 1
BYTE EN 1
BUS COMMAND
1
2
3
45
(I)
(T)
(I)
BYTE EN 2
DATA 2
DATA
TRANSFER #1
NO
DATA
TRANSFERRED
6
(T)
IF BURST
ATTEMPT
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET