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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 65/327頁(yè) |
| 文件大小： | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
11-6
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
11.1.2 Add-On FIFO Status Indicators
The Add-On interface implements FIFO status pins to
indicate the full and empty conditions of the PCI to
Add-On and Add-On to PCI FIFOs. These may be
used by the Add-On to allow data transfers between
the FIFO and memory, a peripheral, or even a cas-
caded external FIFO. The RDEMPTY and WRFULL
status outputs are always available to the Add-On.
Additional status signals are multiplexed with the
byte-wide, non-volatile memory interface pins. If the
S5933 is configured for Add-On initiated bus master-
ing, these status signals also become available to the
Add-On. FIFO status is also indicated by bits in the
Add-On General Control/Status and Bus Master Con-
trol/Status Registers. The table below lists all FIFO
status outputs and their functions.
Signal
Function
RDEMPTY
Indicates empty condition of the PCI to
Add-On FIFO
WRFULL
Indicates full condition of the Add-On
to PCI FIFO
FRF
Indicates full condition of the PCI to
Add-On FIFO (note 1)
FWE
Indicates the empty condition of the
Add-On to PCI FIFO (note 1)
Notes:
1. These signals are only available when a serial non-volatile
memory is used and the device is configured for Add-On initiated
bus mastering (Section 11.3.1).
11.1.3 Add-On FIFO Control Signals
The Add-On interface implements FIFO control pins
to manipulate the S5933 FIFOs. These may be used
by Add-On to control data transfer between the FIFO
and memory, a peripheral, or even a cascaded exter-
nal FIFO. The RDFIFO# and WRFIFO# inputs are
always available. These pins allow direct access to
the FIFO without generating a standard Add-On reg-
ister access using RD#, WR#, SELECT#, address
pins and the byte enables.
Additional control signals are multiplexed with the
byte-wide, non-volatile memory interface pins. If a se-
rial non-volatile memory is used and the S5933 is
configured for Add-On initiated bus mastering, these
control signals also become available. For PCI initi-
ated bus mastering, AMREN, AMWEN, FRC#, and
FWC# functionality is always available through bits in
the Bus Master Control/Status and Add-On General
Control/Status Registers. The FIFO control inputs are
listed below.
Signal
Function
RDFIFO#
Reads data from the PCI to Add-On
FIFO
WRFIFO#
Writes data into the Add-On to PCI
FIFO
FRC#
Reset PCI to Add-On FIFO pointers and
status indicators (note 1)
FWC#
Reset Add-On to PCI FIFO pointers and
status indicators (note 1)
AMREN
Enable bus mastering for Add-On
initiated PCI reads (note 1)
AMWEN
Enable bus mastering for Add-On
initiated PCI writes (note 1)
Notes:
1. These signals are only available when a serial non-volatile
memory is used and the S5933 is configured for Add-On initiated
bus mastering (see Section 11.3.1).
11.1.4 PCI Bus Mastering with the FIFO
The S5933 may initiate PCI bus cycles through the
FIFO interface. The S5933 allows blocks of data to
be transferred to and from the Add-On by specifying
a source/destination address on the PCI bus and a
transfer byte count. This DMA capability allows data
to be transferred across the PCI bus without host
CPU intervention.
Initiating a bus master transfer requires programming
the appropriate address registers and transfer byte
counts. This can be done from either the PCI inter-
face or the Add-On interface (configurable at reset,
see section 11.3.1). Initiating bus master transfers
from the add-on is advantageous because the host
CPU does not have to intervene for the S5933 to
become a PCI Initiator. At the end of a transfer the
S5933 may generate an interrupt to either the PCI
bus (for PCI initiated transfers) or Add-On interface
(for Add-On initiated transfers).
11.1.4.1 Add-On Initiated Bus Mastering
If bit 7 in location 45h of an external serial non-vola-
tile memory is zero, the Master Read Address Regis-
ter (MRAR), Master Write Address Register (MWAR),
Master Read Transfer Count (MRTC), and Master
Write Transfer Count (MWTC) are accessible only
from the Add-On interface. Add-On initiated bus mas-
tering is not possible when a byte-wide boot device is
used due to shared device pins (see Section 11.3.1).
When configured for Add-On initiated bus mastering,
the S5933 transfers data until the transfer count
reaches zero, or it may be configured to ignore the
transfer count.
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