
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-36
ADD-ON DMA CONTROLLER DESIGN FOR THE S5933
To do this, the PLD must decode the addresses for the S5933 bus master address and transfer count registers.
The following S5933 add-on operation register locations must be decoded:
Register
Offset
Bus Master Read Address Register (MRAR)
30h
Bus Master Write Address Register (MWAR)
24h
Bus Master Read Transfer Count (MRTC)
5Ch
Bus Master Write Transfer Count (MWTC)
58h
Add-on bus address lines A6:2 must be decoded. An access to either MRAR or MWAR programs the DMA
address register. It should be noted that MWAR and MRAR are 32-bit registers (as PCI memory space is 4 GB),
only the lower 22 bits are stored by the DMA controller address register (which should be sufficient for most
applications).
An access to either MRTC or MWTC programs the DMA transfer count register. Bit 24 of the DMA controller is
the RWCONT bit (indicating a read or write from the S5933). This bit should be programmed based on which
transfer count register of the S5933 is programmed (indicated by A2).
The following PLD equation modifications are required to implement this function:
/* Inputs */
Pin
=
nSELECT;
/* S5933 SELECT# Input */
/* Logic Equations */
/* For MWTC and MRTC accesses, A2 differentiates between PCI read and write */
/* transfer count registers */
RWCONT.T = LOADC & (RWCONT $ A2.IO);
SEQUENCE slave {
/* Idle State */
present S0
if !nADS.IO & !nSELECT & !HLDA &
((A5.IO & A4.IO & !A3.IO & !A2.IO) #
(A5.IO & !A4.IO & !A3.IO & A2.IO)) next S1;
if !nADS.IO & !nSELECT & !HLDA & A5.IO
next S2;
default next S0;
present S1
/* Address Access Data Phase */
next S3;
present S2
/* Transfer Count Access Data Phase */
next S3;
present S3
/* Recovery Phase */
next S0;
}