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參數(shù)資料
| 型號： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 154/327頁 |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-10
BUS MASTERING WITH THE S5933 PCI MATCHMAKER
If no external non-volatile boot memory is used with
the S5933, the default configuration for bus mastering
is for transfers to be set up by the host CPU. Bits 6
and 5 define how the add-on FIFO interface operates.
The default configuration for FIFO read and write
strobes is to be asynchronous to the PCI clock (pro-
vided to the add-on by the S5933 BPCLK output). For
more information on the FIFO add-on bus interface,
refer to the S5933 PCI Controller Data Book.
3.1.1
PCI Initiated DMA Transfers
If no external non-volatile boot device is used, or if
location 45h, bit 7 is 1, the address and transfer
count registers are only accessible from the PCI bus
interface. This requires that the PCI host write these
register to initiate a DMA transfer. In this configura-
tion, the S5933 can be programmed to generate a
PCI interrupt (INTA#) when the DMA transfer count
reaches zero or when an error occurs during a DMA
transfer (target or master abort conditions).
PCI initiated DMA transfers must be enabled through
the Bus Master Control/Status Register (MCSR).
The register is at offset 3Ch in the S5933 PCI Op-
eration Registers. S5933 Read DMA transfers and
Write DMA transfers have separate control bits and
can be individually enabled. The enable bits are not
automatically cleared upon completion of a DMA
transfer. DMA transfers remain enabled until these
bits are cleared by the host CPU.
3.1.2
Add-on Initiated DMA Transfers
If an external, serial non-volatile boot device is used
and location 45h, bit 7 is 0, the address and transfer
count registers are only accessible from the add-on
bus interface. This requires that add-on logic write
these register to initiate a DMA transfer. In this con-
figuration, the S5933 can be programmed to gener-
ate an add-on interrupt (IRQ#) when the DMA
transfer count reaches zero or when an error occurs
during a DMA transfer. A serial boot device is re-
quired because the transfer enable inputs used for
add-on initiated DMA are multiplexed with the byte-
wide nv-memory interface.
Add-on initiated DMA transfers are enabled using the
AMREN and AMWEN inputs. The bus master enable
bits in the Bus Master Control/Status Register
(MCSR) are ignored. Asserting AMREN enables the
S5933 to request control of the PCI bus for a PCI
read transfer when the appropriate FIFO conditions
are met. Asserting AMWEN enables the S5933 to re-
quest control of the PCI bus for a PCI write transfer
when the appropriate FIFO conditions are met (see
section 3.4 on FIFO management schemes). If an
enable is deasserted during a DMA transfer, the cur-
rent PCI bus transaction completes and the S5933
deasserts REQ#, giving up control of the PCI bus.
3.2
DMA Address Registers
There are two DMA address registers: the Master
Write Address Register (MWAR) and the Master
Read Address Register (MRAR). These registers are
located at offsets 24h and 2Ch, respectively, in the
S5933 PCI Operation Registers. These are written
with the beginning memory address of the DMA
transfer. The S5933 requires that DMA transfers
start on double-word boundaries (A1 and A0 = 0).
During a DMA transfer, the address registers are
incremented by four after each completed data
phase. If a PCI target disconnects and requests a
retry from the S5933, the correct address is main-
tained to allow the transfer to begin from where it
was disconnected.
3.3
DMA Transfer Count Registers
There are two DMA transfer count registers: the
Master Write Transfer Count Register (MWTC) and
the Master Read Transfer Count Register (MRTC).
These registers are located at offsets 28h and 30h,
respectively, in the S5933 PCI Operation Registers.
These are written with the a DMA transfer byte count
of up to 64 Mbytes. The transfer count registers are
decremented by four after each completed data
phase. The transfer count registers do not reset to
their initial value after reaching zero, the PCI host
must reprogram them.
Although S5933 DMA transfer must begin on double-
word boundaries, the transfer count does not have to
be a multiple of four bytes. When the transfer count
decrements below four, only the byte enable corre-
sponding to the number of bytes left are asserted.
For example, if a transfer count of 10 was pro-
grammed into one of the transfer count registers,
two data transfers would complete with all byte en-
ables asserted (8 bytes). The final data transfer
would have only BE0# and BE1# asserted, transfer-
ring the final two bytes.
For add-on initiated DMA transfers, the transfer counts
are enabled or disabled through the Add-on General
Control/Status Register (AGCSTS), bit 28. The transfer
counts for read and write transfers cannot be individu-
ally enabled. This may be useful in applications where
the amount of data to be transferred is not known. If
transfer counts are disabled, the S5933 continues to
transfer data according to the conditions listed above,
but transfer counts are ignored.
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