
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-44
ADD-ON DMA CONTROLLER DESIGN FOR THE S5933
/* Assert CNTC2 when CNTB2 is asserted and A8-15 are set */
CNTC2 = CNTB2 & (A8 & A9 & A10 & A11 & A12 & A13 & A14 & A15);
/* Toggle output when CNT is asserted and all previous bits are
*/
/* ’1' or when a LOAD is performed and the load value (.IO) is
*/
/* different from the existing value. The transfer count is a
*/
/* byte count.
*/
Field XFER_COUNTA = [C7..2];
C2.T = CNT # LOADC & (C2 $ A2.IO);
C3.T = CNT & !C2 # LOADC & (C3 $ A3.IO);
C4.T = CNT & !C2 & !C3 # LOADC & (C4 $ A4.IO);
C5.T = CNT & !C2 & !C3 & !C4 # LOADC & (C5 $ A5.IO);
C6.T = CNT & !C2 & !C3 & !C4 & !C5 # LOADC & (C6 $ A6.IO);
C7.T = CNT & !C2 & !C3 & !C4 & !C5 & !C6 # LOADC & (C7 $ A7.IO);
/* Assert CNTA when CNT is asserted and C2-7 are clear */
CNTA = CNT & !(C2#C3#C4#C5#C6#C7);
Field XFER_COUNTB = [C17..8];
C8.T = CNTA # LOADC & (C8 $ A8.IO);
C9.T = CNTA & !C8 # LOADC & (C9 $ A9.IO);
C10.T = CNTA & !C8 & !C9 # LOADC & (C10 $ A10.IO);
C11.T = CNTA & !C8 & !C9 & !C10 # LOADC & (C11 $ A11.IO);
C12.T = CNTA & !C8 & !C9 & !C10 & !C11 # LOADC & (C12 $ A12.IO);
C13.T = CNTA & !C8 & !C9 & !C10 & !C11 & !C12 # LOADC & (C13 $ A13.IO);
C14.T = CNTA & !C8 & !C9 & !C10 & !C11 & !C12 & !C13 # LOADC & (C14 $ A14.IO);
C15.T
=
CNTA
&
!C8
&
!C9
&
!C10
&
!C11
&
!C12
&
!C13
&
!C14
#
LOADC
&
(C15
$
A15.IO);
C16.T = CNTA & !C8 & !C9 & !C10 & !C11 & !C12 & !C13 & !C14 & !C15 # LOADC & (C16 $
A16.IO);
C17.T = CNTA & !C8 & !C9 & !C10 & !C11 & !C12 & !C13 & !C14 & !C15 & !C16 # LOADC &
(C17 $ A17.IO);
/* This bit identifies a read vs. a write DMA 1 = read, 0 = write */
RWCONT.T = LOADC & (RWCONT $ A24.IO);
FIELD master = [MA2..0];
$DEFINE M0
‘b’000
$DEFINE M1
‘b’001
$DEFINE M2
‘b’011
$DEFINE M3
‘b’010
$DEFINE M4
‘b’110
$DEFINE M5
‘b’111
$DEFINE M6
‘b’101
$DEFINE M7
‘b’100