
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
2-5
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
FIFOs
Two separate FIFO data paths exist within the
S5933. One FIFO handles data movement from the
PCI bus to the Add-On bus (shown in Figure 2-3) and
the other handles movement in the opposite direction
(Figure 2-4). Both of the FIFOs are able to support
PCI bus mastering; each has an address pointer and
transfer count register associated with its PCI bus
transaction. An important feature of the S5933 is the
ability to optionally perform various endian transla-
tions when data is moved through the FIFO. This
feature permits a single Add-On product to maintain
a fixed endian structure within the Add-On while al-
lowing the system platform to operate in its own na-
tive endian format.
Figure 2-3. PCI to Add-On FIFO Concept
Figure 2-4. Add-On to PCI FIFO Concept
READ ADDRESS
REGISTER (WHEN MASTER)
READ TRANSFER
COUNT (WHEN MASTER)
DATA
32
2
32
32 X 8
FIFO
PCI TRANSFER*
FIFO FLAGS
+ CONTROL
READ FIFO
EMPTY STATUS
ADD-ON
FIFO READ CONTROL
FULL STATUS
PCI
DATA
*PCI BUS MEMORY READ = S5933 FIFO WRITE
WHEN S5933 IS BUS MASTER
+1
-1
26 BIT
COUNTER
ZERO DECODE
(STOP)
PCI INTERRUPT
ADD-ON INTERRUPT
PCI
ADDRESS
ENDIAN
CONVERSION
COUNTER
PCI
BUS
INTERFACE
ADD-ON
INTERFACE
WRITE ADDRESS
REGISTER (WHEN MASTER)
WRITE TRANSFER
COUNT (WHEN MASTER)
DATA
32
32 X 8
FIFO
PCI TRANSFER*
FIFO FLAGS
+ CONTROL
WR FULL
ADD-ON
FIFO WRITE
EMPTY
PCI
DATA
*PCI BUS MEMORY WRITE = S5933 FIFO READ
WHEN S5933 IS BUS MASTER
+1
26 BIT
COUNTER
ZERO DECODE
(STOP)
PCI INTERRUPT
ADD-ON INTERRUPT
PCI
ADDRESS
COUNTER
-1
2
PCI
BUS
INTERFACE
ADD-ON
INTERFACE
ENDIAN
CONVERSION