
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121  (619) 450-9333
8-8
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
8.1.4.2 Initiator Preemption
A PCI initiator (bus master) is said to be preempted
when the system platform deasserts the initiator’s
bus grant signal, GNT#, while it still requests the bus
(REQ# asserted). This situation occurs if the
initiator’s latency timer expires and the system plat-
form (bus arbitrator) has a bus master request from
another device. The S5933 Master Latency Timer
register is described in Section 4.8 and controls the
S5933 responsiveness to the removal of a bus grant
(preemption). The presence of a Master Latency
Timer register can cause two preemption situations:
1) Removal of GNT# when the latency timer is
non-zero (S5933 is guaranteed to still “own
the bus”).
2) Removal of the GNT# after the latency timer
has expired.
The first situation is depicted in Figure 8-7, when the
latency timer has not expired. Preemption with a zero
or expired latency timer is shown in Figure 8-8.
Figure 8-7. Master Initiated Termination Due to Preemption and Latency Timer Active (S5933 as Master)
PCI CLOCK
GNT #
FRAME
IRDY#
TRDY#
S5933 LATENCY
TIMER
1
2
3
(T)
(I)
PREEMPTION
DATA
TRANSFERRED
(I)
5
4
DATA
TRANSFERRED
DATA
TRANSFERRED
DATA
TRANSFERRED
6
=3
=2
=1
=0
TIMEOUT
SENSED
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
Figure 8-8. Master Initiated Termination Due to Preemption and Latency Timer Expired (S5933 as Master)
PCI CLOCK
GNT #
FRAME
IRDY#
TRDY#
LATENCY
TIMER
1
2
3
(T)
(I)
PREEMPTION
DATA
TRANSFERRED
(I)
= 0
= 1
5
4
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
S5933