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參數(shù)資料
| 型號： | MT9072 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 62/269頁 |
| 文件大?。?/td> | 778K |
| 代理商： | MT9072 |
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MT9072
Advance Information
62
7.0
Signaling
7.1
T1 Signaling
7.1.1
When global control bit RBEn (Y04, Bit 8) is high the MT9072 will insert ABCD or AB signaling bits into bit 8 of
every transmit DS0 every 6th frame if the corresponding per channel Clear Channel bit(CC) is turned off. For
the transmitter Robbed bit signaling can be turned off on a per channel basis by setting CC bit in per timeslot
control register(Y90-YAF). The AB or ABCD signaling bits from received frames 6 and 12 (AB) or from frames
6, 12, 18 and 24 (ABCD) will be loaded into an internal storage RAM. The transmit AB/ ABCD signaling nibbles
can be set either via the microport or through related channels of the CSTi serial links, see ST-BUS vs.
PCM24 Channel Relationship in Tables 1 to 2. If the MPST bit is set in the Per Timeslot Control register(Y90-
YAF), the transmit signaling is sourced from the microport and not updated from the CSTi channel. If the MPST
bit is not set, any values written to the transmit signaling memory will be overwritten by the CSTi stream.
T1 Robbed Bit Signaling
The receive signaling bits are stored in an internal RAM. These bits can be sourced to the CSTo streams. The
serial control streams that contain the transmit / receive signaling information (CSTi and CSTo respectively)
can be clocked at 2.048 MHz, or 8.192 MHz(global control0 register 900).In the case of 8.192 MHz the
signaling from framers 0 to 3 are sent and received by CSTi0/CSTo0 and framer 4 to 7 are sent and received
on CSTi4/CSTo4. The selection of the CSTi/CSTo interface is done by the number of signaling channels to be
transmitted / received = 24 (timeslots) x 4 bits per timeslot (ABCD) = 24 nibbles. This leaves many unused
nibble positions in the 2.048 MHz CSTi / CSTo bandwidth. These unused nibble locations are tristated. The
usage of the bit stream is as follows: the signaling bits are inserted / reported in the same CSTi / CSTo
channels that correspond to the DS1 channels used in DSTi / DSTo - see Table 1 to 2. The ABCD are in the
least significant nibble of each channel. Unused nibbles and timeslots are tristate. In order to facilitate
multiplexing on the CSTo control stream, an additional control bit CSToEn (bit 1 of the interrupt and IO Control
Word YF1) will tristate the whole stream when set low. This control bit is forced low when the reset pin is
asserted. In the case of D4 trunks, only AB bits are reported. The control bits SM1-0(Register Y04) allow the
user to program the 2 unused bits reported on CSTo in the signaling nibble(for D4 Mode) otherwise occupied
by CD signaling bits in ESF trunks.
A receive signaling bit debounce of 6 msec can be selected (RSDB set high - bit 6 of the signaling Control
Word Y04) for all T1 Modes.
If multiframe synchronization is lost (Synchronization and Alarm Status Word(Y10) Bit 12, MFSYNC = 1), the
receive signaling bits are frozen. They will become unfrozen when multi - frame synchronization is acquired
(this is the same as terminal frame synchronization for ESF links).
When the CASRI interrupt is unmasked, IRQ will become active when a signaling state change is detected in
any of the 24 receive channels and a selectable 1 msec, 4 msec or 8 msec timer(Y04 bit 0,1) has expired. This
function helps to reduce the frequency of interrupts generated due to signaling changes. For instance if 7
channels had a signaling change only one interrupt will be generated in a 1, 4 or 8 msec duration. Upon an
interrupt the user has to read the CAS registers(Y70 to Y87)to determine the channels with a signaling
change.The CASRIM interrupt mask is located in register Y45 bit 2 (reset low to enable interrupt); and the
CASRI interrupt status bit in register is Y35 bit 2. Any channels marked as clear channels will not generate an
interrupt due to changes in ABCD bits.
When bit 0 (CC) in the per timeslot control word (Y90 to YA7) is set no bit robbing for the purpose of signaling
will occur in this channel and no signaling change interrupts will be generated by the channel. When bit 7
(MPST) is set, the transmit signaling for the addressed channel can only be programmed by writing to the
transmit signaling page (Y50 to Y67) via the microport. If MPST is zero, the transmit signaling information is
constantly updated with the information from the equivalent channel on CSTi.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
| MT9072AV2 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 220BGA - Trays |
| MT90732 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS E2/E3 Framer (E2/E3F) |
| MT90732AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS E2/E3 Framer (E2/E3F) |
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