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參數(shù)資料
| 型號(hào)： | MT9072 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 209/269頁(yè) |
| 文件大?。?/td> | 778K |
| 代理商： | MT9072 |
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Advance Information
MT9072
209
16.2.10 Timeslot 0-31 Control Registers (Y90 - YAF) Bit Functions
Table 191 describes the bit functions of each (32 registers in total, one register for each timeslot) of the
Timeslot Control Registers in the MT9072. Each register is repeated for each of the 8 framers. Framer 0 is
addressed with Y=0, Framer 1 with Y=1, Framer 2 with Y=2 and so on up to Framer 7 with Y=7 (where Y
represents the 4 most significant address bits (MSB) A11-A8). In addition, a simultaneous write to all 8 framers
is possible by setting the MSB address to Y=8 (1000). Note that timeslots 0 to 15 are accommodated by
addresses Y90 to Y9F respectively, and timeslots 16 to 31 are accommodated by addresses YA0 to YAF
respectively.
A (0), (1) or (#) in the “Name” column of these tables indicates the state of the data bits after a reset (RESET,
RSTC or RST). The (#) indicates that a (0) or (1) is possible.
Bit
Name
Functional Description
15-10
(#### ####) not used.
9
RADI(n)
(0)
Receive Alternate Digit Inversion.
the data received on DSTo timeslot n from the
received PCM30 link timeslot n has every second bit inverted. If zero, this bit has no effect
on channel data.
8
MPDR
(0)
Micro Port Data Receive.
Setting this bit freezes the receive data for a given channel
After putting the freeze the data (Y09).
7
CASS(n)
(0)
Channel Associated Signaling (CAS) Source.
Selects the source for the CAS data
(A,B,C,D) on the transmit PCM30 link in bit positions one to four, and five to eight of
timeslot 16 in frames 1 to 15. If zero, ST-BUS (CSTi) is selected as the source. If one, data
register (register address Y5,6n) is selected as the source. For n=1 to 15, the CASS(n) bit
corresponds to timeslot n which corresponds to channel n. For n=17 to 31, the CASS(n)
bit corresponds to timeslot n which corresponds to channel n-1.
6
TADI(n)
(0)
Transmit Alternate Digit Inversion.
If one, the data sourced from DSTi timeslot n (n = 0
to 31) to the transmit PCM30 link timeslot n has every second bit inverted, If zero, this bit
has no effect on channel data.
5
RTSL(n)
(0)
Remote Timeslot Loopback.
If one, the data from the received PCM30 link timeslot n (n
= 0 to 31) is output on DSTo timeslot n and is also looped back to the transmit PCM30 link
timeslot n. If zero, the loopback is disabled.
4
LTSL(n)
(0)
Local Timeslot Loopback.
If one, the data sourced from DSTi timeslot n (n = 0 to 31) to
the transmit PCM30 link timeslot n is also looped back to DSTo timeslot n. If zero, this
loopback is disabled.
3
TTST(n)
(0)
Transmit Test.
If one and control bit ADSEQ (register address Y01) is one, the A-law
digital milliwatt will be transmitted in PCM30 timeslot n. When one and ADSEQ is zero, a
Pseudo-Random Bit Sequence (PRBS 2
15
-1) will be transmitted in PCM30 timeslot n.
More than one timeslot may be activated at once. If zero, neither of these test signals will
be connected to timeslot n.
2
RRST(n)
(0)
Receive Test.
If one and control bit ADSEQ (register address Y01) is one, the A-law
digital milliwatt will be transmitted in DSTo timeslot n. When one and ADSEQ is zero, a
Pseudo Random Bit Sequence (PRBS 2
15
-1) receiver will be connected to DSTo timeslot
n. This receiver circuit will synchronize to the transmit PRBS signal and perform a bit
comparison of the two sequences. If zero, neither of these test signals will be connected to
the corresponding timeslot.
1
MPDT(0)
Micro Port Data Transmit.
Setting this bit allows for the transmit data for a given channel
to be replaced by the idle code(Y0A). The idle code can be written by the micro port for
trunck conditioning applications. The data in Y0A will replace the appropriate PCM30
channel.
0
(#)
not used.
Note: For address Y90 (n=0), set all control bits to 0.
Table 191 - Timeslot (TS) n (n = 0 to 31) Control Register (Address Y90 (TS0) to YAF(TS31)) (E1)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
| MT9072AV2 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 220BGA - Trays |
| MT90732 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS E2/E3 Framer (E2/E3F) |
| MT90732AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS E2/E3 Framer (E2/E3F) |
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