
MT9072
Advance Information
xxviii
9.0
MT9072 Access and Control.........................................................................................74
9.1
Processor Interface (A11-A0, D15-D0, I/M, DS, R/W, CS, IRQ, Pins)................................................... 74
9.1.1
Framer and Register Access........................................................................................................... 74
9.1.1.1 CS and IRQ ............................................................................................................................... 75
9.1.2
ST-BUS Interface (DSTi, DSTo, CSTi, CSTo Pins)......................................................................... 75
9.1.3
IMA Interface (DSTi, DSTo, Pins).................................................................................................... 75
9.1.4
Signaling Multiframe Boundary (RxMF, TxMF Pins) ...................................................................... 76
9.1.5
Control Pins..................................................................................................................................... 76
9.1.5.1 Reset Operation (RESET Pin, RST Bit and RSTC Bit).............................................................. 76
9.1.5.2 Transmit AIS Operation (TAIS Pin)............................................................................................ 78
9.1.5.3 IEEE 1149.1-1990 Test Access Port (TAP)............................................................................... 79
9.1.6
Data Link (DL) Interface (RxDL, RxDLC, TxDL, TxDLC Pins)......................................................... 79
9.1.7
Multiframe Boundary (RxMF, TxMF Pins)....................................................................................... 79
10.0 ST-BUS Analyzer............................................................................................................79
11.0 Loopbacks .....................................................................................................................79
11.1 T1 Loopbacks......................................................................................................................................... 79
11.2 T1 In Band Loopback Codes.................................................................................................................. 81
11.3 E1 Loopbacks......................................................................................................................................... 82
12.0 Performance Monitoring...............................................................................................84
12.1 T1 Error Counters................................................................................................................................... 84
12.2 E1 Error Counters ................................................................................................................................. 84
13.0 Maintenance and Alarms..............................................................................................86
13.1 T1 Maintenance and Alarms .................................................................................................................. 86
13.1.1
T1 Error Insertion............................................................................................................................. 86
13.1.2
T1 Per Timeslot Control................................................................................................................... 86
13.1.3
T1 Per Timeslot Looping ................................................................................................................. 86
13.1.4
T1 Pseudo-Random Bit Sequence (PRBS) Testing........................................................................ 86
13.1.5
T1 Mu-law Milliwatt.......................................................................................................................... 87
13.1.6
T1 Alarms........................................................................................................................................ 88
13.1.7
T1 Per Timeslot Trunk Conditioning................................................................................................ 89
13.2 E1 Maintenance and Alarms.................................................................................................................. 89
13.2.1
E1 Error Insertion ............................................................................................................................ 90
13.2.2
E1 Per Timeslot Control .................................................................................................................. 90
13.2.3
E1 Per Timeslot Looping................................................................................................................. 90
Table of Contents (continued)