
MT9072
Advance Information
xxvi
1.0
Overview ........................................................................................................................38
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10 Performance Monitoring and Debugging................................................................................................ 39
Standards Compliance........................................................................................................................... 38
Microprocessor Port............................................................................................................................... 38
Interface to the Physical Layer Device................................................................................................... 38
Interface to the System Backplane......................................................................................................... 38
Framing Modes ...................................................................................................................................... 38
Access to the Maintenance Channel...................................................................................................... 39
Robbed Bit Signaling/Channel Associated Signaling............................................................................. 39
Common Channel Signaling................................................................................................................... 39
HDLCs.................................................................................................................................................... 39
2.0
PCM24 Interface (T1).....................................................................................................40
2.1
2.2
2.3
2.4
T1 Interface to the System Backplane ................................................................................................... 40
T1 Interface to the Physical Layer Device............................................................................................. 42
T1 Line Coding...................................................................................................................................... 42
T1 Pulse Density................................................................................................................................... 42
3.0
PCM30 Interface (E1).....................................................................................................42
3.1
3.2
E1 Interface to the System Backplane................................................................................................... 42
E1 Interface to the Physical Layer Device.............................................................................................. 44
4.0
Framing ..........................................................................................................................44
4.1
T1 Framing............................................................................................................................................. 44
4.1.1
T1 D4 Framing................................................................................................................................. 45
4.1.2
T1 ESF Framing.............................................................................................................................. 46
4.1.3
T1 T1DM Framing ........................................................................................................................... 47
4.1.4
T1 G.802 Mode................................................................................................................................ 47
4.2
E1 Framing............................................................................................................................................. 48
4.2.1
E1 Basic Framing (Timeslot 0)........................................................................................................ 49
4.2.2
E1 CRC-4 Multiframing (Timeslot 0)................................................................................................ 49
4.2.2.1 E1 Automatic CRC-4 Interworking............................................................................................. 51
4.2.3
E1 Channel Associated Signaling (CAS) Multiframing (Timeslot 16).............................................. 51
4.2.4
E1 Framing Algorithm...................................................................................................................... 51
4.2.4.1 Notes for Synchronization State Diagram (Figure 7)................................................................ 52
5.0
Elastic Buffer .................................................................................................................53
5.1
Transmit Elastic Buffer........................................................................................................................... 55
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