
Advance Information
MT9072
177
Bit
Name
Functional Description
15
14
13
#
not used.
Sa4 Source Select.
These 2 bits determine the source of the transmit Sa4 bits in timeslot 0 of
NFAS frames.
Select Bits:
Sa4 Source
00
Transmit National Data Register (YB0)
01
TxDL pin (received Sa4 bits are sent to the RxDL pin)
10
DSTi pin (ST-BUS Channel 0, Bit 4 in NFAS frames)
11
HDLC (Transmit and Receive Sa4 bits)
Note the received Sa4 bits are always available in the RX National Data Bit Buffer (YC0) and
timeslot 0 on the DSTo pin.
Sa5 Source Select.
These 2 bits determine the source of the transmit Sa5 bits in
timeslot 0 of NFAS frames.
Select Bits: Sa5 Source
00
Transmit National Data Register (YB1)
01
TxDL pin (received Sa5 bits are sent to the RxDL pin)
10
DSTi pin (ST-BUS Channel 0, Bit 3 in NFAS frames)
11
HDLC (Transmit and Receive Sa5 bits)
Note the received Sa5 bits are always available in the RX National Data Bit Buffer (YC1) and
timeslot 0 on the DSTo pin.
Sa6 Source Select.
These 2 bits determine the source of the transmit Sa6 bits in
timeslot 0 of NFAS frames.
Select Bits:
Sa6 Source
00
Transmit National Data Register (YB2)
01
TxDL pin (received Sa6 bits are sent to the RxDL pin)
10
DSTi pin (ST-BUS Channel 0, bit 2 in NFAS frames)
11
HDLC (Transmit and Receive Sa6 bits)
Note the received Sa6 bits are always available in the RX National Data Bit Buffer (YC2) and
timeslot 0 on the DSTo pin.
Sa7 Source Select.
These 2 bits determine the source of the transmit Sa7 bits in
timeslot 0 of NFAS frames.
Select Bits:
Sa7 Source
00
Transmit National Data Register (YB3)
01
TxDL pin (received Sa7 bits are sent to the RxDL pin)
10
DSTi pin (ST-BUS Channel 0, Bit 1 in NFAS frames)
11
HDLC (Transmit and Receive Sa7 bits)
Note the received Sa7 bits are always available in the RX National Data Bit Buffer (YC3) and
timeslot 0 on the DSTo pin.
Sa8 Source Select.
These 2 bits determine the source of the transmit Sa8 bits in timeslot 0 of
NFAS frames.
Select Bits:
Sa8 Source
00
Transmit National Data Register (YB4)
01
TxDL pin (received Sa8 bits are sent to the RxDL pin)
10
DSTi pin (ST-BUS Channel 0, Bit 1 in NFAS frames)
11
HDLC (Transmit and Receive Sa8 bits)
Note the received Sa8 bits are always available to the RX National Data Bit Buffer (YC4) and
timeslot 0 on the DSto pin.
not used.
Table 154 - DataLink Control Register (R/W Address Y08) (E1)
Sa4SS
(00)
14
13
Sa5SS
(00)
10
9
Sa6SS
(00)
8
7
Sa7SS
(00)
6
5
Sa8SS
(00)
4-2
#