
MT9072
Advance Information
200
Bit
Name
Functional Description
15
#
not used.
14
Sa5VI
Sa5 Value Bit Interrupt.
This bit is one when the corresponding latched status bit (Sa5VL,
register address Y26) is set, and the corresponding mask bit is unmasked (Sa5VM, register
address Y46). This bit is cleared when either this register, or the latched status register is read.
13
12
11
10
Sa6V3I
Sa6V2I
Sa6V1I
Sa6V0I
Sa6 Value Bits 3-0 Interrupt.
This bit is one when the corresponding latched status bit
(Sa6V*L, register address Y26) is set, and the corresponding mask bit is unmasked (Sa6V*M,
register address Y46). This bit is cleared when either this register, or the latched status register
is read.
9
Sa6N8I
Eight Consecutive Sa6 Nibbles Interrupt.
This bit is one when the corresponding latched
status bit (Sa6N8L, register address Y26) is set, and the corresponding mask bit is unmasked
(Sa6N8M, register address Y46). This bit is cleared when either this register, or the latched
status register is read.
8
Sa6NI
Sa6 Nibble Change Interrupt.
This bit is one when the corresponding latched status bit
(Sa6NL, register address Y26) is set, and the corresponding mask bit is unmasked (Sa6NM,
register address Y46). This bit is cleared when either this register, or the latched status register
is read.
7
SaNI
Sa Nibble Change Interrupt.
This bit is one when the corresponding latched status bit (SaNL,
register address Y26) is set, and the corresponding mask bit is unmasked (SaNM, register
address Y46). This bit is cleared when either this register, or the latched status register is read.
6
Sa5TI
Sa5 Bit Change Interrupt.
This bit is one when the corresponding latched status bit (Sa5TL,
register address Y26) is set, and the corresponding mask bit is unmasked (Sa5TM, register
address Y46). This bit is cleared when either this register, or the latched status register is read.
5
SaTI
Sa Bit Change Interrupt.
This bit is one when the corresponding latched status bit (SaTL,
register address Y26) is set, and the corresponding mask bit is unmasked (SaTM, register
address Y46). This bit is cleared when either this register, or the latched status register is read.
4
CASRI
Receive Channel Associated Signaling (CAS) Interrupt.
is bit is one when the
corresponding latched status bit (CASRL, register address Y24) is set, and the corresponding
mask bit is unmasked (CASRM, register address Y44). This bit is cleared when either this
register, or the latched status register is read.
3
CALNI
CRC-4 Alignment 2ms Timer Interrupt.
This bit is one when the corresponding latched status
bit (CALNL, register address Y26) is set, and the corresponding mask bit is unmasked
(CALNM, register address Y46). This bit is cleared when either this register, or the latched
status register is read.
2
T2I
Timer 2 Interrupt.
This bit is one when the corresponding latched status bit (T2L, register
address Y26) is set, and the corresponding mask bit is unmasked (T2M, register address Y46).
This bit is cleared when either this register, or the latched status register is read.
1
T1I
Timer 1 Interrupt.
This bit is one when the corresponding latched status bit (T1L, register
address Y26) is set, and the corresponding mask bit is unmasked (T1M, register address Y46).
This bit is cleared when either this register, or the latched status register is read.
0
ONESECI
One Second Timer Status Interrupt.
This bit is one when the corresponding latched status bit
(ONESECL, register address Y26) is set, and the corresponding mask bit is unmasked
(ONESECM, register address Y46). This bit is cleared when either this register, or the latched
status register is read.
Table 184 - CAS, National, CRC-4 Local and Timer Interrupt Status Register (Address Y36) (E1)