
Advance Information
MT9072
xxix
13.2.4
13.2.5
13.2.6
13.2.7
E1 Pseudo-Random Bit Sequence (PRBS) Testing........................................................................ 90
E1 A-law Milliwatt ............................................................................................................................ 91
E1 Alarms........................................................................................................................................ 91
E1 Automatic Alarms....................................................................................................................... 92
14.0 Interrupts........................................................................................................................92
14.1 Interrupt Status Register Overview ........................................................................................................ 93
14.1.1
Interrupt Related Control Bits and Pins........................................................................................... 94
14.2 Interrupt Servicing Methods ................................................................................................................... 94
14.2.1
Polling Method................................................................................................................................. 94
14.2.2
Vector Method................................................................................................................................. 94
14.3 T1 Interrupt Vector and Interrupt Source Summary ............................................................................... 95
14.4 E1 Interrupt Vector and Interrupt Source Summary............................................................................... 96
14.5 E1 Interrupt Source and Interrupt Status Register Summary................................................................. 98
15.0 JTAG (Joint Test Action Group) Operation .................................................................99
15.1 Test Access Port (TAP)........................................................................................................................ 100
15.2 Test Access Port (TAP) Controller ....................................................................................................... 101
15.3 Instruction Register .............................................................................................................................. 101
15.4 JTAG Data Registers ........................................................................................................................... 101
15.4.1
Identification Register.................................................................................................................... 101
15.4.2
The Bypass Register..................................................................................................................... 102
15.5 Boundary Scan Description Language (BSDL) File ............................................................................. 102
16.0 MT9072 Register Set ...................................................................................................103
16.1 T1 Register Set .................................................................................................................................... 103
16.1.1
Register Address (000 - FFF) Summaries..................................................................................... 103
16.1.1.1 Framer Address (0XX-9XX) Summary .................................................................................. 103
16.1.1.2 Register Group Address (Y00 - YFF) Summary.................................................................... 104
16.1.1.3 Global Control and Status Register (900-91F) Summary...................................................... 105
16.1.1.4 Master Control Registers Address (Y00-Y0F, YF0 to YFF) Summary .................................. 106
16.1.1.5 Master Status Registers Address (Y10-Y1F) Summary ........................................................ 108
16.1.1.6 Latched Status Registers Address (Y20-Y2F) Summary ...................................................... 109
16.1.1.7 Interrupt Status Registers Address (Y30-Y3F) Summary...................................................... 110
16.1.1.8 Interrupt Mask Registers Address (Y40-Y4F) Summary ....................................................... 111
16.1.2 Master Control Registers (Y00 to Y0F ) Bit Functions.................................................................. 112
16.1.3
Master Status Registers(Y10-Y18)Bit Functions........................................................................... 122
16.1.4
Latched Status Registers (Y20 - Y2F) Bit Functions..................................................................... 128
16.1.5 Interrupt Status Registers (Y30 - Y3F) Bit Functions.................................................................... 133
16.1.6 Interrupt Mask Registers (Y40 - Y4F) Bit Functions ..................................................................... 137
Table of Contents (continued)