
Advance Information
MT9072
193
2
T2L
Timer 2 Latch.
When the CRC-4 T2 (10ms) status bit (register address Y11) toggles from
zero to one, this status bit is latched to one. This bit is set on a basic frame (FPi) basis. This
bit is cleared when either this register, or the corresponding interrupt status register (register
address Y36) is read.
1
T1L
Timer 1 Latch.
When the CRC-4 T1 (100ms) status bit (register address Y11) toggles from
zero to one, this status bit is latched to one. This bit is set on a basic frame (FPi) basis. This
bit is cleared when either this register, or the corresponding interrupt status register (register
address Y36) is read.
0
ONESECL
One Second Timer Status Latch.
When the ONESEC status bit (register address Y11)
toggles from zero to one, this status bit is latched to one. This bit is set on a basic frame (FPi)
basis. This bit is cleared when either this register, or the corresponding interrupt status
register (register address Y36) is read.
Bit
Name
Functional Description
15-4
#
not used.
3
RAIP
Remote Alarm Indication Status Persistent Latch.
When the RAI (A) status bit (register
address Y12 and Y13) toggles from zero to one, this status bit is latched to one. This bit is
cleared when this register is read while the RAI status bit is zero.
2
AISP
Alarm Indication Status Signal Persistent.
When the AIS status bit (register address
Y12) toggles from zero to one, this status bit is latched to one. This bit is cleared when this
register is read while the AIS status bit is zero.
1
LOSSP
Loss of Signal Status Indication Persistent Latch.
When the LOSS status bit (register
address Y12) toggles from zero to one, this status bit is latched to one. This bit is cleared
when this register is read while the LOSS status bit is zero.
0
BSYNCP
Receive Basic Frame Alignment Persistent Latch.
When the BSYNC status bit (register
address Y10) toggles from zero to one, this status bit is latched to one. This bit is cleared
when this register is read while the BSYNC status bit is zero.
Table 176 - Performance Persistent Latched Status Register (Address Y27) (E1)
Bit
Name
Functional Description
Table 175 - CAS, National, CRC-4 Local and Timer Latched Status Register (Address Y26) (E1)