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參數(shù)資料
| 型號(hào)： | XRT86SH328IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | DATACOM, FRAMER, PBGA568 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-568 |
| 文件頁(yè)數(shù)： | 88/339頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | XRT86SH328IB |
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XRT86SH328
PRELIMINARY
78
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
the last read of this register. The Receive STS-1/STS-3 TOH Processor block will generate this interrupt anytime it has
accepted a new Section Trace Message within the incoming STS-1/STS-3 data-stream.
`
0 - Indicates that the New Section Trace Message Interrupt has not occurred since the last read of this register.
`
1 - Indicates that the New Section Trace Message Interrupt has occurred since the last read of this register.
N
OTE
:
The user can read out the contents of the Receive Section Trace Message Buffer, which is located at Address
Locations 0x0400 through 0x04FF).
BIT 3 - Change in Section Trace Message Mismatch Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change in Section Trace Mismatch Defect Condition
interrupt has occurred since the last read of this register. The Receive STS-1/STS-3 TOH Processor block will generate
this interrupt in response to either of the following events.· Whenever the Receive STS-1/STS-3 TOH Processor block
declares the Section Trace Message Mismatch defect condition· Whenever the Receive STS-1/STS-3 TOH Processor
block clears the Section Trace Mismatch defect condition.
`
0 - Indicates that the Change in Section Trace Message Mismatch Defect Condition interrupt has not occurred since
the last read of this register.
`
1 - Indicates that the Change in Section Trace Message Mismatch Defect Condition interrupt has occurred since the
last read of this register.
N
OTE
:
The user can determine whether the Section Trace Message Mismatch condition is currently cleared or
declared by reading the state of BIT 2 (Section Trace Message Mismatch Defect Declared) within the Receive
STS-1/STS-3 Transport Status Register - Byte 1 (Address Location= 0x0206).
BIT 2 - Unused
BIT 1 - Change in K1, K2 Byte Unstable Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change in K1, K2 Byte Unstable Defect Condition
interrupt has occurred since the last read of this register. The Receive STS-1/STS-3 TOH Processor block will generate
this interrupt in response to either of the following events.
Whenever the Receive STS-1/STS-3 TOH Processor block declares the K1, K2 Byte Unstable Defect
condition.
Whenever the Receive STS-1/STS-3 TOH Processor block clears the K1, K2 Byte Unstable Defect condition.
`
0 - Indicates that the Change of K1, K2 Byte Unstable Defect Condition interrupt has NOT occurred since the last read
of this register.
`
1 - Indicates that the Change of K1, K2 Byte Unstable Defect Condition interrupt has occurred since the last read of
this register.
N
OTE
:
The user can determine whether the K1, K2 Byte Unstable Defect Condition is currently being declared or
cleared by reading out the contents of BIT 5 (K1, K2 Byte Unstable Defect Declared), within the Receive STS-
1/STS-3 Transport Status Register - Byte 0 (Address Location= 0x0207).
BIT 0 - New K1, K2 Byte Value Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the New K1, K2 Byte Value Interrupt has occurred since the
last read of this register. The Receive STS-1/STS-3 TOH Processor block will generate this interrupt whenever its has
accepted a new set of K1, K2 byte values from the incoming STS-1/STS-3 data-stream
`
0 - Indicates that the New K1, K2 Byte Value Interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the New K1, K2 Byte Value Interrupt has occurred since the last read of this register.
N
OTE
:
The user can obtain the contents of the new K1 byte by reading out the contents of the Receive STS-1/STS-3
Transport K1 Byte Value Register (Address Location= 0xN11F). Further, the user can also obtain the contents
of the new K2 byte by reading out the contents of the Receive STS-1/STS-3 Transport K2 Byte Value Register
(Address Location= 0x0223).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL32_1 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32_2 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86SH328IB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Multiplexer Voyager RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86SH328OR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86VL30 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION |
| XRT86VL30_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL |
| XRT86VL30_1 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
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