
XRT86SH328
PRELIMINARY
50
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT 7 - Unused
BIT 6 - Receive STS-1/STS-3 TOH Processor Block Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Receive STS-1/STS-3 TOH Processor Block for
interrupt generation.
If the user writes a 0 to this register bit and disables the Receive STS-1/STS-3 TOH Processor Block (for interrupt
generation), then all Receive STS-1/STS-3 TOH Processor Block interrupts will be disabled for interrupt generation.
If the user writes a 1 to this register bit, the user will still need to enable the individual Receive STS-1/STS-3 TOH
Processor Block interrupt(s) at the Source Level in order to enable that particular interrupt.
`
0 - Disables all Receive STS-1/STS-3 TOH Processor Block interrupts within the device.
`
1 - Enables the Receive STS-1/STS-3 TOH Processor Block at the Block Level for interrupt generation.
BIT 5 - Receive STS-1/STS-3 POH Processor Block Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Receive STS-1/STS-3 POH Processor Block for
interrupt generation.
If the user writes a 0 into this register bit and disables the Receive STS-1/STS-3 POH Processor Block (for interrupt
generation), then all Receive STS-1/STS-3 Processor Block interrupts will be disabled for interrupt generation.
If the user writes a 1 to this register bit, then the user will still need to enable the individual Receive STS-1/STS-3 POH
Processor Block Interrupt(s) at the Source Level in order to enable that particular interrupt.
`
0 - Disables all Receive STS-1/STS-3 POH Processor Block Interrupts within the device.
`
1 - Enables the Receive STS-1/STS-3 POH Processor Block at the Block Level for interrupt generation.
BIT [4:3] - Unused
BIT 2 - External Interrupt Input Pin # 1 - Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the External Interrupt Pin # 1 Interrupt.
If this interrupt is enabled, then the XRT86SH328 will generate an interrupt anytime that the EXT_INT_1 input pin (Ball
T5) has been driven to the logic HIGH level.
`
0 - Disables the External Interrupt Input # 1 Interrupt
`
1 - Enables the External Interrupt Input # 1 Interrupt.
BIT [1:0] - Unused
T
ABLE
37: O
PERATION
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
- B
YTE
0 (A
DDRESS
= 0
X
0017)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Receive
STS-1/STS-3
TOHBlock
Interrupt
Enable
Receive
STS-1 POH
Block
Interrupt
Enable
Unused
External
Interrupt
Enable # 1
Unused
R/O
R/W
R/W
R/O
R/O
R/W
R/W
R/O
0
0
0
0
0
0
0
0