
PRELIMINARY
XRT86SH328
275
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
N
OTE
:
If one of these transmit HDLC buffers contain a message which has yet to be completely read in and processed
for transmission by the transmit HDLC controller, then this bit will automatically reflect the value corresponding
to the next available buffer when it is read. Changing this bit to the in use buffer is not permitted.
BIT [6:0] - Transmit HDLC Message Byte Count:
The exact function of these bits depends on whether the transmit HDLC controller is configured to transmit MOS or BOS
messages to the remote terminal equipment.
In BOS Mode:
These bit fields contain the number of repetitions the BOS message must be transmitted before the transmit HDLC
controller generates the transmit end of transfer (TxEOT) interrupt and halts transmission. If these fields are set to
0000000, then the BOS message will be transmitted for an indefinite number of times.
In MOS Mode:
These bit fields contain the length, in number of octets, of the message to be transmitted. The length of MOS message
specified in these bits include header bytes such as the SAPI, TEI, and Control Field. However, it does not include the
FCS bytes.
BIT7 - Receive HDLC Buffer Pointer:
This bit identifies which receive HDLC buffer contains the most recently received HDLC message.
`
0 = Indicates that receive HDLC buffer 0 contains the contents of the most recently received HDLC message.
`
1 = Indicates that receive HDLC buffer 1 contains the contents of the most recently received HDLC message.
BIT [6:0] - Receive HDLC Message Byte Count:
The exact function of these bits depends on whether the receive HDLC controller is configured to receive MOS or BOS
messages.
In BOS Mode:
These seven bits contain the number of repetitions the BOS message must be received before the receive HDLC
controller generates the receive end of transfer (RxEOT) interrupt. If these bits are set to 0000000, the message will be
received indefinitely and no RxEOT interrupt will be generated.
In MOS Mode:
These seven bits contain the size in bytes of the HDLC message that has been received and written into the receive
HDLC buffer. The length of MOS message shown in these bits include header bytes such as the SAPI, TEI, Control
Field, and the FCS bytes.
BIT [3:2] - CI Alarm Transmit (Only in ESF)
These two bits are used to enable or disable AIS-CI or RAI-CI generation in T1 ESF mode only. AIS-CI and RAI-CI are
T
ABLE
409: T1 F
RAMER
B
LOCK
- R
ECEIVE
D
ATA
L
INK
C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
N115,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RBUFPTR
Receive HDLC Message Byte Count
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
410: T1 F
RAMER
B
LOCK
- C
USTOMER
I
NSTALLATION
A
LARM
G
ENERATION
R
EGISTERS
(A
DDRESS
=
0
X
N11C,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Customer Installation Alarm
Generation[1:0]
Customer Installation Alarm
Detection[1:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0