
PRELIMINARY
XRT86SH328
95
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT [7:0] - SD_SET_THRESHOLD - MSB
These READ/WRITE bits, along the contents of the Receive STS-1/STS-3 Transport - SD SET Threshold - Byte 0
registers are used to specify the number of B2 byte (or BIP-24) errors that will cause the Receive STS-1/STS-3 TOH
Processor block to declare the SD (Signal Degrade) defect condition.
When the Receive STS-1/STS-3 TOH Processor block is checking for declaring the SD defect condition, it will
accumulate B2 byte (or BIP-24) errors throughout the SD Defect Declaration Monitoring Period. If the number of
accumulated B2 byte (or BIP-24) errors exceeds that value, which is programmed into this and the Receive STS-1/STS-
3 Transport SD SET Threshold - Byte 0 register, then the Receive STS-1/STS-3 TOH Processor block will declare the
SD defect condition.
BIT [7:0] - SD_SET_THRESHOLD - LSB
These READ/WRITE bits, along the contents of the Receive STS-1/STS-3 Transport - SD SET Threshold - Byte 1
registers are used to specify the number of B2 byte (or BIP-24) errors that will cause the Receive STS-1/STS-3 TOH
Processor block to declare an SD (Signal Degrade) defect condition.
When the Receive STS-1/STS-3 TOH Processor block is checking for declaring the SD defect condition, it will
accumulate B2 byte (or BIP-24) errors throughout the SD Defect Monitoring Period. If the number of accumulated B2
byte (or BIP-24) errors exceeds that which has been programmed into this and the Receive STS-1/STS-3 Transport SD
SET Threshold - Byte 1 register, then the Receive STS-1/STS-3 TOH Processor block will declare the SD defect
condition.
BIT [7:0] - SD_CLEAR_THRESHOLD - MSB
These READ/WRITE bits, along the contents of the Receive STS-1/STS-3 Transport - SD CLEAR Threshold - Byte 0
registers are used to specify the upper limit for the number of B2 byte (or BIP-24) errors that will cause the Receive
STS-1/STS-3 TOH Processor block to clear the SD (Signal Degrade) defect condition.
When the Receive STS-1/STS-3 TOH Processor block is checking for clearing the SD defect condition, it will
accumulate B2 byte (or BIP-24) errors throughout the SD Defect Clearance Monitoring Period. If the number of
accumulated B2 byte (or BIP-24) errors is less than that programmed into this and the Receive STS-1/STS-3 Transport
T
ABLE
110: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- R
ECEIVE
SD SET T
HRESHOLD
- B
YTE
1 (A
DDRESS
L
OCATION
=
0
X
0242)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
T
ABLE
111: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- R
ECEIVE
SD SET T
HRESHOLD
- B
YTE
0 (A
DDRESS
L
OCATION
=
0
X
0243)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
T
ABLE
112: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- R
ECEIVE
SD CLEAR T
HRESHOLD
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
0246)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1