
XRT86SH328
PRELIMINARY
150
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT [7:0] - Transmit H4 Byte Value
These READ/WRITE bit-fields are used to have software control over the value of the H4 byte, within each outbound
STS-1/STS-3 SPE.
If the user configures the Transmit STS-1/STS-3 POH Processor block to this register as the source of the H4 byte, then
it will automatically write the contents of this register into the H4 byte location, within each outbound STS-1/STS-3 SPE.
This feature is enabled whenever the user writes a 0 into BIT 0 (H4 Insertion Type) within the Transmit STS-1/STS-3
Path - SONET Control Register - Byte 1 register (Address Location= 0x07A7).
BIT [7:0] - Transmit Z3 Byte Value
These READ/WRITE bit-fields are used to have software control over the value of the Z3 byte, within each outbound
STS-1/STS-3 SPE.If the user configures the Transmit STS-1/STS-3 POH Processor block to this register as the source
of the Z3 byte, then it will automatically write the contents of this register into the Z3 byte location, within each outbound
STS-1/STS-3 SPE.
This feature is enabled whenever the user writes a 0 into BIT 1 (Z3 Insertion Type) within the Transmit STS-1/STS-3
Path - SONET Control Register - Byte 0 register (Address Location= 0x0782).
BIT [7:0] - Transmit Z4 Byte Value
These READ/WRITE bit-fields are used to have software control over the value of the Z4 byte, within each outbound
STS-1/STS-3 SPE.
If the user configures the Transmit STS-1/STS-3 POH Processor block to this register as the source of the Z4 byte, then
it will automatically write the contents of this register into the Z4 byte location, within each outbound STS-1/STS-3 SPE.
This feature is enabled whenever the user writes a 0 into BIT 2 (Z4 Insertion Type) within the Transmit STS-1/STS-3
Path - SONET Control Register - Byte 0 register (Address Location= 0x0782).
T
ABLE
198: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
H4 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07A7)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_H4_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
199: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
Z3 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
=
0
X
07AB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_Z3_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
200: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
Z4 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
=
0
X
N9AF)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_Z4_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0