
XRT86SH328
PRELIMINARY
56
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
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1 - Configures this particular XRT86SH328 to function as the Slot Master.
N
OTES
:
1.
This bit-field is only value if (1) the Telecom Bus Interface is configured to operate in the STS-3/STS-
1/STS-3 Mode.
2.
The XRT86SH328 has been configured to operate in the Fractional Bandwidth Mode.
3.
This particular XRT86SH328 has been assigned the STS-1/STS-3 Time Slot of [0, 0].
BIT [4:3] - STS-1/STS-3 Time Slot Assignmen
This READ/WRITE bit-field is used to specify which STS-1/STS-3 Time-slot that the XRT86SH328 will fill-in, if it has
been configured to operate in the Fractional Bandwidth Mode.
Valid values to write into these bit-fields are: [0, 0], [0, 1], and [1, 0].
N
OTES
:
1.
These bit-fields are only active if (1) the Telecom Bus Interface has been configured to operate in the
STS-3/STS-1/STS-3 Mode, and (2) if the user has configured the XRT86SH328 to operate in the Fractional
Bandwidth Mode.2.
2.
If a given XRT86SH328 has been designed into a given STS-3/STS-1/STS-3 application (which involves
a total of three XRT86SH328s), for the XRT86SH328 (which has been designated as the Slot Master), the
user MUST set these bit-fields to [0, 0].
BIT 2 - Telecom Bus Parity Include V1 Signal
BIT 1 - .Telecom Bus Interface - Frame Pulse Mode
This READ/WRITE bit-field is used to configure the STS-1/STS-3 Telecom Bus Interface to operate in the Frame Pulse
Mode. If the user configures the STS-1/STS-3 Telecom Bus Interface to operate in the Frame Pulse Mode, then all of
the following will be true.
The TxA_C1J1V1_FP output pin will only pulse high coincident to whenever the XRT86SH328 outputs the
very first byte of a given STS-1/STS-3 frame via the Transmit STS-1/STS-3 Telecom Bus Interface - Output
Data Bus (TxA_D[7:0])
The RxD_C1J1V1_FP input pin will accept a pulse, coincident to whenever the very first byte of the incoming
STS-1/STS-3 frame is being placed on the Receive STS-1/STS-3 Telecom Bus Interface - Input Data Bus
(RxD_D[7:0]).
If the user does NOT configure the STS-1/STS-3 Telecom Bus Interface to operate in the Frame Pulse Mode, then the
Telecom Bus Interface will perform as configured in Bits 0 (Telecom Bus - V1 Signal Support Enable) within this register,
and BIT 3 (Telecom Bus J1 Only) within the STS-3/STS-1/STS-3 Telecom Bus Control Register - Byte 0.
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0 - Configures the STS-1/STS-3 Telecom Bus Interface to NOT operate in the Frame Pulse Mode
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1 - Configures the STS-1/STS-3 Telecom Bus Interface to operate in the Frame Pulse Mode
BIT 0 - Transmit STS-1/STS-3 Telecom Bus - V1 Pulse Enable
This READ/WRITE bit-field is used to configure the Transmit STS-1/STS-3 Telecom Bus Interface to pulse the
TxA_C1J1V1_FP output pin HIGH coincident to whenever the XRT86SH328 outputs a V1 byte via the Transmit STS-
1/STS-3 Telecom Bus Interface - Output Data Bus (TxA_D[7:0])
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.0 - Configures the Transmit STS-1/STS-3 Telecom Bus Interface to NOT denote the V1 byte via the
TxA_C1J1V1_FP output pin.
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1 - Configures the Transmit STS-1/STS-3 Telecom Bus Interface to denote the V1 byte via the TxA_C1J1V1_FP
output pin.
N
OTE
:
This register bit is only active if the XRT86SH328 has been configured to VT/TU map T1/E1 data into
SONET/SDH.