
XRT86SH328
PRELIMINARY
158
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
(in the outbound STS-1 or STS-3 Data-stream) since the last read of this register.
N
OTE
:
This register contains the MSB (Most Significant Bits) of this 16-bit expression.
BIT [7:0] - Transmit Negative Pointer Adjustment Count - LSB
This RESET-upon-READ register, along with the Transmit Negative Pointer Adjustment Count Register - Byte 1
presents a 16-bit representation of the number of Negative (or Decrementing) Pointer Adjustments that have occurred
(in the outbound STS-1 or STS-3 Data-stream) since the last read of this register.
N
OTE
:
This register contains the LSB (Least Significant Bits) of this 16-bit expression.
BIT [7:0] - Transmit Positive Pointer Adjustment Count - MSB
This RESET-upon-READ register, along with the Transmit Positive Pointer Adjustment Count Register - Byte 0 presents
a 16-bit representation of the number of Positive (or Incrementing) Pointer Adjustments that have occurred (in the
outbound STS-1 or STS-3 Data-stream) since the last read of this register.
N
OTE
:
This register contains the MSB (Most Significant Bits) of this 16-bit expression.
BIT [7:0] - Transmit Positive Pointer Adjustment Count - LSB
This RESET-upon-READ register, along with the Transmit Positive Pointer Adjustment Count Register - Byte 1 presents
a 16-bit representation of the number of Positive (or Incrementing) Pointer Adjustments that have occurred (in the
outbound STS-1 or STS-3 Data-stream) since the last read of this register.
N
OTE
:
This register contains the LSB (Least Significant Bits) of this 16-bit expression.
to here 1/12/07
2.8
Transmit TUG-3 MAPPER/VC-4 POH Processor Block Registers (SDH/TUG-3 Applications
Only)
The register map for the Transmit TU-3 Mapper/VC-4 POH Processor block is presented an discussed in detail
within the "SDH Version of the Register Map".
T
ABLE
213: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
N
EGATIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
07D1)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_Negative_Pointer_Adjustment_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
214: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
P
OSITIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
07D2)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_Positive_Pointer_Adjustment_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
215: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
P
OSITIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
07D3)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_Positive_Pointer_Adjustment_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0