
XRT86SH328
PRELIMINARY
224
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT [7:0] - PMON FEBE Event Count[15:8]:
These RESET-upon-READ bits, along with that within the PMON FEBE Event Count Register - LSB combine to reflect
the cumulative number of FEBE/REI events that the Receive DS3 Framer block has detected within the incoming DS3
data-stream, since the last read of this register. This register contains the Most Significant byte of this 16-expression.
BIT [7:0] - PMON FEBE Event Count[7:0]:
These RESET-upon-READ bits, along with that within the PMON FEBE Event Count Register - MSB combine to reflect
the cumulative number of FEBE/REI events that the Receive DS3 Framer block has detected within the incoming DS3
data-stream, since the last read of this register. This register contains the Least Significant byte of this 16-expression.
BIT [7:0] - PMON CP-Bit Error Count[15:8]:
These RESET-upon-READ bits, along with that within the DS3 Framer Block - PMON CP-Bit Error Count Register - LSB
combine to reflect the cumulative number of CP bit errors that the Receive DS3 Framer block has detected since the
last read of this register. This register contains the Most Significant byte of this 16-bit expression.
N
OTE
:
These register bits are not active if the Transmit and Receive DS3 Framer blocks have NOT been configured to
support the DS3 C-bit Parity Framing format.
BIT [7:0] - PMON CP-Bit Error Count[7:0]:
These RESET-upon-READ bits, along with that within the DS3 Framer Block - PMON CP-Bit Error Count Register -
MSB combine to reflect the cumulative number of CP bit errors that the Receive DS3 Framer block has detected since
the last read of this register. This register contains the Least Significant byte of this 16-bit expression.
T
ABLE
306: DS3 F
RAMER
B
LOCK
- PMON FEBE E
VENT
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
0E56)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_FEBE_Event_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
307: DS3 F
RAMER
B
LOCK
- PMON FEBE E
VENT
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
0E57)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_FEBE_Event_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
308: DS3 F
RAMER
B
LOCK
- CP-B
IT
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
0E58)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_CP_Bit_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
309: DS3 F
RAMER
B
LOCK
- CP-B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
0E59)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_CP_Bit_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0