
XRT86SH328
PRELIMINARY
180
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
WRITE access (to the Microprocessor Interface), if a Loss of Receive Clock Event were to occur.
The intent behind this feature is to prevent any READ/WRITE accesses (to the DS3 Framer blocks) from hanging in the
event of a Loss of Clock event.
`
0 - Enables the Receive Loss of Clock feature.
`
1 - Disables the Receive Loss of Clock feature
Bits 4 -3 - Unused
BIT 2 - Transmit Line Clock Invert
This READ/WRITE bit-field is used to configure the Transmit DS3 Framer block to update the TxDS3POS and
TxDS3NEG output pins upon either the rising or falling edge of TxDS3LineClk.
`
0 - Configures the Transmit DS3 Framer block to update the TxDS3POS/TxDS3NEG upon the rising edge of the
TxDS3LineClk. The user should insure that the LIU IC will sample TxDS3POS/TxDS3NEG upon the falling edge of
TxDS3LineClk.
`
1 - Configures the Transmit DS3 Framer block to update the TxDS3POS/TxDS3NEG upon the falling edge of the
TxDS3LineClk. The user should insure that the LIU IC will sample TxDS3POS/TxDS3NEG upon the rising edge of
TxDS3LineClk.
BIT 1 - Receive Line Clock Invert
This READ/WRITE bit-field is used to configure Receive DS3 Framer block to sample and latch the
RxDS3POS/RxDS3NEG input pins upon either the rising or falling edge of RxDS3LineClk.
`
0 - Configures the Receive DS3 Framer block to sample the RxDS3POS/RxDS3NEG input pins upon the falling edge
of the RxDS3LineClk input signal.
`
1 - Configures the Receive DS3 Framer block to sample the RxDS3POS/RxDS3NEG input pins upon the rising edge
of the RxDS3LineClk input signal.
BIT 0 - Receive DS3 Framer Block - Reframe Command
A 0 to 1 transition, within this bit-field commands the Receive DS3 Framer block to exit the Frame Maintenance Mode,
and go back and enter the Frame Acquisition Mode.
N
OTE
:
The user should go back and set this bit-field to 0 following execute of the Reframe Command.
Bit 7 - Receive DS3 Framer Bock Interrupt Enable:
This READ/WRITE bit-field is used to enable or disable the Receive DS3 Framer Block for Interrupt Generation. If the
user enables the Receive DS3 Framer block (for Interrupt Generation) at the block level, the user still needs to enable
the interrupts at the Source Level, as well, in order for these interrupt to be enabled.
However, if the user disables the Receive DS3 Framer block (for Interrupt Generation) at the Block Level, then ALL
Receive DS3 Framer-related blocks are disabled.
`
0 - Disables all Receive DS3 Framer blocks interrupts.
`
1 - Enables the Receive DS3 Framer block for Interrupt Generation (at the Block Level)
Bits 6 - 5 - Unused:
Bit 4 - M13 MUX Block Interrupt Enable:
This READ/WRITE bit-field is used to enable or disable the M13 MUX block for Interrupt Generation. If the user enables
T
ABLE
240: DS3 F
RAMER
B
LOCK
- B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
0E04)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Receive DS3
Framer
Block
Interrupt
Enable
Unused
M13 MUX
Block Inter-
rupt Enable
Unused
Transmit
DS3 Framer
Block
Interrupt
Enable
One Second
Interrupt
Enable
R/W
R/O
R/O
R/W
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0