
XRT86SH328
PRELIMINARY
114
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
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1 - Indicates that the Detection of B3 Byte Error Interrupt has occurred since the last read of this interrupt.
BIT 6 - Detection of New Pointer Interrupt Status
This RESET-upon-READ indicates whether the Detection of New Pointer interrupt has occurred since the last read of
this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects
a new pointer value in the incoming STS-1/STS-3 frame.
N
OTE
:
Pointer Adjustments with NDF will not generate this interrupt.
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0 - Indicates that the Detection of New Pointer Interrupt has NOT occurred since the last read of this register.
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1 - Indicates that the Detection of New Pointer Interrupt has occurred since the last read of this register.
BIT 5 - Detection of Unknown Pointer Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Detection of Unknown Pointer interrupt has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime that it
detects a pointer that does not fit into any of the following categories.
An Increment Pointer
A Decrement Pointer
An NDF Pointer
An AIS (e.g., All Ones) Pointer
New Pointer
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0 - Indicates that the Detection of Unknown Pointer interrupt has NOT occurred since the last read of this register.
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1 - Indicates that the Detection of Unknown Pointer interrupt has occurred since the last read of this register.
BIT 4 - Detection of Pointer Decrement Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Detection of Pointer Decrement Interrupt has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects
a Pointer Decrement event.
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0 - Indicates that the Detection of Pointer Decrement interrupt has NOT occurred since the last read of this register.
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1 - Indicates that the Detection of Pointer Decrement interrupt has occurred since the last read of this register.
BIT 3 - Detection of Pointer Increment Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Detection of Pointer Increment Interrupt has occurred
since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will
generate an interrupt anytime it detects a Pointer Increment event.
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0 - Indicates that the Detection of Pointer Increment interrupt has NOT occurred since the last read of this register.
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1 - Indicates that the Detection of Pointer Increment interrupt has occurred since the last read of this register.
BIT 2 - Detection of NDF Pointer Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Detection of NDF Pointer interrupt has occurred since
the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects
an NDF Pointer event.
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0 - Indicates that the Detection of NDF Pointer interrupt has NOT occurred since the last read of this register.
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1 - Indicates that the Detection of NDF Pointer interrupt has occurred since the last read of this register.
BIT 1 - Change of LOP-P Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change in LOP-P Defect Condition interrupt has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either
of the following events.
When the Receive STS-1 POH Processor block declares the LOP-P defect condition.