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參數(shù)資料
| 型號(hào)： | XRT86SH328IB |
| 廠商： | EXAR CORP |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | DATACOM, FRAMER, PBGA568 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-568 |
| 文件頁(yè)數(shù)： | 119/339頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | XRT86SH328IB |
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PRELIMINARY
XRT86SH328
109
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
value.Note:Receiving a given C2 byte value in 3 (or 5) consecutive SPEs also sets this bit-field to 0.
`
0 - Indicates that the Receive STS-1 POH Processor block is currently NOT declaring the C2 (Path Signal Label Byte)
Unstable defect condition.
`
1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the C2 (Path Signal Label Byte)
Unstable defect condition.
BIT 5 - Path - Unequipped (UNEQ-P) Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the
UNEQ-P defect condition. The Receive STS-1 POH Processor block will declare the UNEQ-P defect condition, anytime
that it receives at least five (5) consecutive STS-1/STS-3 frames, in which the C2 byte was set to the value 0x00 (which
indicates that the SPE is Unequipped).
The Receive STS-1 POH Processor block will clear the UNEQ-P defect condition, if it receives at least five (5)
consecutive STS-1/STS-3 frames, in which the C2 byte was set to a value other than 0x00.
`
0 - Indicates that the Receive STS-1 POH Processor block is currently NOT declaring the UNEQ-P defect condition.
`
1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the UNEQ-P defect condition.
N
OTE
:
:The Receive STS-1 POH Processor block will not declare the UNEQ-P defect condition if it configured to
expect to receive STS-1/STS-3 frames with C2 bytes being set to 0x00 (e.g., if the Receive STS-1 Path -
Expected Path Label Value Register -Address Location= 0x0297) is set to 0x00.
BIT 4 - Path Payload Mismatch (PLM-P) Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the
PLM-P defect condition.The Receive STS-1 POH Processor block will declare the PLM-P defect condition, if it receives
at least five (5) consecutive STS-1/STS-3 frames, in which the C2 byte was set to a value other than that which it is
expecting to receive. Whenever the Receive STS-1 POH Processor block is determining whether or not it should
declare the PLM-P defect, it will check the contents of the following two registers.
The Receive STS-1 Path - Received Path Label Value Register (Address Location= 0xN196).
The Receive STS-1 Path - Expected Path Label Value Register (Address Location= 0xN197).
The Receive STS-1 Path - Expected Path Label Value Register contains the value of the C2 bytes, that the Receive
STS-1 POH Processor blocks expects to receive.The Receive STS-1 Path - Received Path Label Value Register
contains the value of the C2 byte, that the Receive STS-1 POH Processor block has most received validated (by
receiving this same C2 byte in five consecutive STS-1/STS-3 frames). The Receive STS-1 POH Processor block will
declare the PLM-P defect condition if the contents of these two register do not match. The Receive STS-1 POH
Processor block will clear the PLM-P defect condition if whenever the contents of these two registers do match.
`
0 - Indicates that the Receive STS-1 POH Processor block is currently NOT declaring the PLM-P defect condition.
`
1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the PLM-P defect condition
N
OTE
:
The Receive STS-1 POH Processor block will clear the PLM-P defect, upon declaring the UNEQ-P defect
condition.
BIT 3 - Path Remote Defect Indicator (RDI-P) Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the
RDI-P defect condition.
If the Receive STS-1 POH Processor block is configured to support the Single-bit RDI-P function, then it will declare
the RDI-P defect condition if BIT 5 (within the G1 byte of the incoming STS-1/STS-3 frame) is set to 1 for RDI-P_THRD
number of incoming consecutive STS-1/STS-3 frames.
If the Receive STS-1 POH Processor block is configured to support the Enhanced RDI-P (ERDI-P) function, then it will
declare the RDI-P defect condition if Bits 5, 6 and 7 (within the G1 byte of the incoming STS-1/STS-3 frame) are set to
[0, 1, 0], [1, 0, 1] or [1, 1, 0] for RDI-P_THRD number of consecutive STS-1/STS-3 frames.
`
0 - Indicates that the Receive STS-1 POH Processor block is NOT currently declaring the RDI-P defect condition.
`
1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the RDI-P defect condition.
N
OTE
:
The user can specify the value for RDI-P_THRD by writing the appropriate data into Bits 3 through 0 (RDI-P
THRD) within the Receive STS-1 Path - SONET Receive RDI-P Register (Address Location= 0x0293).
BIT 2 - RDI-P (Path - Remote Defect Indicator) Unstable Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the
RDI-P Unstable defect condition. The Receive STS-1 POH Processor block will declare a RDI-P I Unstable defect
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL32_1 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32_2 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86SH328IB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Multiplexer Voyager RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86SH328OR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86VL30 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION |
| XRT86VL30_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL |
| XRT86VL30_1 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
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