
PRELIMINARY
XRT86SH328
287
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT [7:0] LAPD Buffer 0:
This register is used to transmit and receive LAPD messages within buffer 0 of the HDLC controller. Users should
determine the next available buffer by reading the BUFAVAL bit (BIT7 of the Transmit Data Link Byte Count Register
0xN114h). If buffer 0 is available, writing to buffer 0 will insert the message into the outgoing LAPD frame after the LAPD
message is sent and the data from the transmit buffer cannot be retrieved.
After detecting the receive end of transfer interrupt (RxEOT), users should read the RBUFPTR bit (bit 7 of the receive
data link byte count register 0xN115h) to determine which buffer contains the received LAPD message ready to be read.
If RBUFPTR bit indicates that buffer 0 is available to be read, reading buffer 0 continuously will retrieve the entire
received LAPD message.
N
OTE
:
When writing to or reading from Buffer 0, the register is automatically incremented such that the entire 64 Byte
LAPD message can be written into or read from buffer 0 continuously.
BIT [7:0] LAPD Buffer 1:
This register is used to transmit and receive LAPD messages within buffer 1 of the HDLC controller. Users should
determine the next available buffer by reading the BUFAVAL bit (BIT7 of the Transmit Data Link Byte Count Register
0xN114h). If buffer 1 is available, writing to buffer 1 will insert the message into the outgoing LAPD frame after the LAPD
message is sent and the data from the transmit buffer cannot be retrieved.
After detecting the receive end of transfer interrupt (RxEOT), users should read the RBUFPTR bit (bit 7 of the receive
data link byte count register 0xN115h) to determine which buffer contains the received LAPD message ready to be read.
If RBUFPTR bit indicates that buffer 1 is available to be read, reading buffer 1 continuously will retrieve the entire
received LAPD message.
N
OTE
:
When writing to or reading from Buffer 1, the register is automatically incremented such that the entire 64 Byte
LAPD message can be written into or read from buffer 1 continuously.
T
ABLE
424: T1 F
RAMER
B
LOCK
- LAPD B
UFFER
0 C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
N600 - 0
X
N640,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LAPD Buffer 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
425: T1 F
RAMER
B
LOCK
- LAPD B
UFFER
1 C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
N700 - 0
X
N740,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LAPD Buffer 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0