
PRELIMINARY
XRT86SH328
157
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT [7:5] - LOP-P (Path - Loss of Pointer) - RDI-P Code
These three READ/WRITE bit-fields are used to specify the value that the Transmit STS-1/STS-3 POH Processor block
will transmit, within the RDI-P bit-fields of the G1 byte (within the outbound STS-1/STS-3 SPE), whenever the
corresponding Receive STS-1/STS-3 POH Processor block detects and declares a LOP-P condition.
To enable this feature, the user must set BIT 4 (RDI-P upon LOP-P) within this register to 1.
BIT 4 - Transmit RDI-P upon LOP-P
This READ/WRITE bit-field is used to configure the Transmit STS-1/STS-3 POH Processor block to automatically
transmit the RDI-P Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive
STS-1/STS-3 POH Processor block declares a LOP-P condition
`
0 - Disables the automatic transmission of RDI-P upon detection of LOP-P.
`
1 - Enables the automatic transmission of RDI-P upon detection of LOP-P.
BIT[3:1]AIS-P (Path - AIS) - RDI-P Code
These three READ/WRITE bit-fields are used to specify the value that the Transmit STS-1/STS-3 POH Processor block
will transmit, within the RDI-P bit-fields of the G1 byte (within the outbound STS-1/STS-3 SPE), whenever the
corresponding Receive STS-1/STS-3 POH Processor block detects and declares an AIS-P condition.
To enable this feature, the user must set BIT 4 (RDI-P upon AIS-P) within this register to 1.
BIT 0 - Transmit RDI-P upon AIS-P
This READ/WRITE bit-field is used to configure the Transmit STS-1/STS-3 POH Processor block to automatically
transmit the RDI-P Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive
STS-1/STS-3 POH Processor block declares a AIS-P condition.
`
0 - Disables the automatic transmission of RDI-P upon detection of AIS-P.
`
1 - Enables the automatic transmission of RDI-P upon detection of AIS-P.
BIT [7:4] - Unused
BIT 3:0] - TxPOHClk Output Clock Signal Speed
These READ/WRITE bit-fields are used to specify the frequency of the TxPOHClk output clock signal. The formula that
relates the contents of these register bits to the TxPOHClk frequency is presented below.
FREQ = 51.84 /[2 * (TxPOH_CLOCK_SPEED + 1)
For STS-3/STS-1/STS-3 applications, the frequency of the RxPOHClk output signal must be in the range of 2.36MHz
to 25.92MHz
BIT [7:0] - Transmit Negative Pointer Adjustment Count - MSB
This RESET-upon-READ register, along with the Transmit Negative Pointer Adjustment Count Register - Byte 0
presents a 16-bit representation of the number of Negative (or Decrementing) Pointer Adjustments that have occurred
T
ABLE
211: T
RANSMIT
STS-1/STS-3 P
ATH
- S
ERIAL
P
ORT
C
ONTROL
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07CF)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
TxPOH Clock Speed[4:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
212: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
N
EGATIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
07D0)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_Negative_Pointer_Adjustment_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0