
XRT86SH328
PRELIMINARY
308
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT7 - RFI-V Defect Declared:
This READ/WRITE bit-field indicates whether or not the Receive VT-De-Mapper Block is currently declaring the RFI-V
defect condition.
`
0 - Indicates that the Receive VT-De-Mapper Block is NOT currently declaring the RFI-V defect condition.
`
1 - Indicates that the Receive VT-De-Mapper Block is currently declaring the RFI-V defect condition.
BIT6 - RDI-V Defect Declared:
This READ/WRITE bit-field indicates whether or not the Receive VT-De-Mapper Block is currently declaring the RDI-V
defect condition.
`
0 - Indicates that the Receive VT-De-Mapper Block is NOT currently declaring the RDI-V defect condition.
`
1 - Indicates that the Receive VT-De-Mapper Block is currently declaring the RDI-V defect condition.
BIT 5 - Force DS1/E1 AIS In Egress Direction
This READ/WRITE bit-field is used to configure this particular Receive VT-De-Mapper block to transmit the DS1/E1 AIS
indicator within the Egress Direction of this particular DS1/E1 Channel.
`
0 - Configures the Receive VT-De-Mapper Block to NOT transmit the DS1/E1 AIS Pattern within the Egress Direction
corresponding to this particular channel.
`
1 - Configures the Receive VT-De-Mapper block to transmit the DS1/E1 AIS Pattern within the Egress Direction
corresponding to this particular channel.
Figure 21
presents an illustration of the Functional Block Diagram of the XRT86SH328, whenever the VT-De-Mapper
block has been configured to overwrite the contents within the corresponding DS1/E1 channel with the DS1/E1 AIS
pattern (as it is being de-mapped from the VT1.5 or VT2 data-stream by the VT De-Mapper block.
F
IGURE
21. A
N
I
LLUSTRATION
OF
THE
F
UNCTIONAL
B
LOCK
D
IAGRAM
OF
THE
XRT86SH328,
WHENEVER
THE
VT-
D
E
-M
APPER
BLOCK
(
ASSOCIATED
WITH
A
GIVEN
CHANNEL
)
OVERWRITES
THE
CONTENTS
OF
A
DE
-
MAPPED
DS1/E1
SIGNAL
WITH
THE
DS1/E1 AIS P
ATTERN
STS-1/
STS-3
Telecom
Bus
Interface
Transmit
STS-1/3
TOH
Processor
Block
Receive
STS-1/3
TOH
Processor
Block
Transmit
STS-1 POH
Processor
Block
Receive
STS-1 POH
Processor
Block
VT/TU
De-Mapper
Block
Receive
DS3
Framer
Block
Transmit
DS3
Framer
Block
M23
MUX
Block
M23
De-MUX
Block
Ingress
Direction
Receive
DS1/E1
Framer
Block
Egress
Direction
Receive
DS1/E1
Framer
Block
Ingress
Direction
Transmit
DS1/E1
Framer
Block
Egress
Direction
Transmit
DS1/E1
Framer
Block
Receive
DS1/E1
LIU
Block
Transmit
DS1/E1
LIU
Block
DS3/
STS-1
LIU
Interface
M12
MUX
Block
M12
De-MUX
Block
DS1/E1
Jitter
Atten
Block
DS1/E1 Channel 0
DS1/E1 Channel 0
DS2 Channel 0
From DS1/E1 Channels 1 - 27
From DS2 Channels 1 - 6
To DS2 Channels 1 - 6
From DS1/E1 Channels 1 - 3
To DS1/E1 Channels 1 - 3
To DS1/E1
Channels 1 - 27
VT/TU
Mapper
Block
DS2 Channel 0
DS1/E1 AIS