
PRELIMINARY
XRT86SH328
317
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
Bits 7 - 6 - Unused:
Bit 5 - Change of VT Path Trace Message Unstable Defect Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the "Change of VT Path Trace Message Unstable Defect
Condition" Interrupt has occurred since the last read of this register. The VT-De-Mapper block will generate this interrupt
in response to either of the following conditions.
Whenever the VT-De-Mapper block declares the "VT Path Trace Message Unstable" Defect condition.
Whenever the VT De-Mapper block clears the "VT Path Trace Message Unstable" Defect condition.
`
0 - Indicates that the "Change of VT Path Trace Message Unstable Defect Condition" Interrupt has NOT occurred
since the last read of this register.
`
1 - Indicates that the "Change of VT Path Trace Message Unstable Defect Condition" Interrupt has occurred since
the last read of this register.
Bit 4 - New VT Path Trace Message Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the "New VT Path Trace Message" Interrupt has occurred
since the last read of this register. The VT-De-Mapper block will generate this interrupt whenever it has "accepted" a
new "VT Path Trace Message" via the incoming VT-data-stream.
`
0 - Indicates that the "New VT Path Trace Message" Interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the "New VT Path Trace Message" Interrupt has occurred since the last read of this register.
Bit 3 - Change of TIM-V Defect Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the "VT-De-Mapper" block has generated the "Change of
TIM-V Defect Condition" interrupt since the last read of this register. The VT-De-Mapper block will generate this
interrupt in response to either of the following conditions.
Whenever it declares the TIM-V Defect condition.
Whenever it clears the TIM-V Defect condition.
`
0 - Indicates that the "Change of TIM-V Defect Condition" interrupt has NOT occurred since the last read of this
register.
`
1 - Indicates that the "Change of TIM-V Defect Condition" interrupt has occurred since the last read of this register.
Bits 2 - 0 - Unused:
T
ABLE
454: C
HANNEL
C
ONTROL
- VT-M
APPER
B
LOCK
- E
GRESS
D
IRECTION
- I
NTERRUPT
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
ND67,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
1C)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Change of
VT Path
Trace
Message
Unstable
Defect
Condition
Interrupt
Status
New VT Path
Trace
Message
Interrupt
Status
Change of
TIM-V
Defect
Condition
Interrupt
Status
Unused
R/O
R/O
RUR
RUR
RUR
R/O
R/O
R/O
0
0
0
0
0
0
0
0