
PRELIMINARY
XRT86SH328
223
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT [7:0]: PMON Framing Bit ErrorCount[15:8]:
These RESET-upon-READ bits, along with that within the DS3 Framer Block - PMON Framing Bit Error Count Register
- LSB combine to reflect the cumulative number of Framing bit errors that the Receive DS3 Framer block has detected
since the last read of this register. This register contains the Most Significant byte of this 16-bit expression.
N
OTE
:
The Receive DS3 Framer block will increment this register each time that it detects F or M bit errors within the
incoming DS3 data-stream.
BIT [7:0]: PMON Framing Bit ErrorCount[7:0]:
These RESET-upon-READ bits, along with that within the DS3 Framer Block - PMON Framing Bit Error Count Register
- MSB combine to reflect the cumulative number of Framing bit errors that the Receive DS3 Framer block has detected
since the last read of this register. This register contains the Least Significant byte of this 16-bit expression.
N
OTE
:
The Receive DS3 Framer block will increment this register each time that it detects F or M bit errors within the
incoming DS3 data-stream.
BIT [7:0]: PMON P-Bit Error Count[15:8]:
These RESET-upon-READ bits, along with that within the DS3 Framer Block - PMON P-bit Error Count Register - LSB
combine to reflect the cumulative number of P-bit errors that the Receive DS3 Framer block has detected within the
incoming DS3 data-stream, since the last read of this register. This register contains the Most Significant byte of this
16-bit expression.
BIT [7:0] - PMON P-Bit Error Count[7:0]:
These RESET-upon-READ bits, along with that within the DS3 Framer Block - PMON P-bit Error Count Register - MSB
combine to reflect the cumulative number of P-bit errors that the Receive DS3 Framer block has detected within the
incoming DS3 data-stream, since the last read of this register. This register contains the Least Significant byte of this
16-bit expression.
T
ABLE
303: DS3 F
RAMER
B
LOCK
- PMON F
RAMING
B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
0E53)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_Framing_Bit_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
304: DS3 F
RAMER
B
LOCK
- PMON P-B
IT
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
0E54)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_P_Bit _Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
305: DS3 F
RAMER
B
LOCK
- PMON P-B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
0E55)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON_P_Bit_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0