
PRELIMINARY
XRT86SH328
155
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT [7:4] - Unused
BIT [3:1] - PLM-P (Path - Payload Mismatch) - RDI-P Code
These three READ/WRITE bit-fields are used to specify the value that the Transmit STS-1/STS-3 POH Processor block
will transmit, within the RDI-P bit-fields of the G1 byte (within the outbound STS-1/STS-3 SPE), whenever the
corresponding Receive STS-1/STS-3 POH Processor block detects and declares a PLM-P condition. In order to enable
this feature, the user must set BIT 0 (RDI-P upon PLM-P) within this register to 1.
BIT 0 - Transmit RDI-P upon PLM-P
This READ/WRITE bit-field is used to configure the Transmit STS-1/STS-3 POH Processor block to automatically
transmit the RDI-P Code (as configured in Bits 3 through 1 - within this register) whenever the corresponding Receive
STS-1/STS-3 POH Processor block declares a PLM-P condition.
`
0 - Disables the automatic transmission of RDI-P upon detection of PLM-P.
`
1 - Enables the automatic transmission of RDI-P upon detection of PLM-P.
BIT [7:5] - TIM-P (Path - Trace Identification Message Mismatch) - RDI-P Code
These three READ/WRITE bit-fields are used to specify the value that the Transmit STS-1/STS-3 POH Processor block
will transmit within the RDI-P bit-fields of the G1 byte (within the outbound STS-1/STS-3 SPE), whenever the Receive
STS-1/STS-3 POH Processor block detects and declares the TIM-P defect condition.
To enable this feature, the user must set BIT 4 (Transmit RDI-P upon TIM-P) within this register to 1.
BIT 4 - Transmit RDI-P upon TIM-P
This READ/WRITE bit-field is used to configure the Transmit STS-1/STS-3 POH Processor block to automatically
transmit the RDI-P Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive
STS-1/STS-3 POH Processor block declares the TIM-P defect condition.
`
0 - Disables the automatic transmission of RDI-P upon detection of TIM-P.
`
1 - Enables the automatic transmission of RDI-P upon detection of TIM-P.
BIT [3:1] - UNEQ-P (Path - Unequipped) - RDI-P Code
These three READ/WRITE bit-fields are used to specify the value that the Transmit STS-1/STS-3 POH Processor block
will transmit, within the RDI-P bit-fields of the G1 byte (within the outbound STS-1/STS-3 SPE), whenever the Receive
STS-1/STS-3 POH Processor block detects and declares the UNEQ-P defect condition.
To enable this feature, the user must set BIT 0 (Transmit RDI-P upon UNEQ-P) within this register to 1.
BIT 0 - Transmit RDI-P upon UNEQ-P
T
ABLE
208: T
RANSMIT
STS-1/STS-3 P
ATH
- RDI-P C
ONTROL
R
EGISTER
- B
YTE
2 (A
DDRESS
L
OCATION
= 0
X
07C9)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
PLM-P RDI-P Code[2:0]
Transmit
RDI-P upon
PLM-P
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
209: T
RANSMIT
STS-1/STS-3 P
ATH
- RDI-P C
ONTROL
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
07CA)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TIM-P RDI-P Code[2:0]
Transmit
RDI-P upon
TIM -P
UNEQ-P RDI-P Code[2:0]
Transmit
RDI-P upon
UNEQ-P
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0