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參數(shù)資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 9/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標準包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 17 of 82
March 20, 2007 – Revision 1.01
The bridge does not respond to special cycle transactions. The bridge cannot guarantee delivery of
a special cycle transaction to downstream buses because of the broadcast nature of the special cycle
command and the inability to control the transaction as a target. To generate special cycle
transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must
be used.
The bridge neither generates Type 0 configuration transactions on the primary PCI bus nor
responds to Type 0 configuration transactions on the secondary PCI buses.
2.2
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus
command is driven on P_CBE[3:0]. The bridge supports the linear increment address mode only, which
is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is
nonzero, the bridge automatically disconnects the transaction after the first data transfer.
2.3
DEVICE SELECT (DEVSEL#) GENERATION
The bridge always performs positive address decoding (medium decode) when accepting transactions
on either the primary or secondary buses. The bridge never does subtractive decode.
2.4
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases. A data phase is
completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data occurs only
when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a
transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or
when IRDY# and STOP# are asserted. See Section 2.8 for further discussion of transaction termination.
Depending on the command type, the bridge can support multiple data phase PCI transactions. For
detailed descriptions of how the bridge imposes disconnect boundaries, see Section 2.5.4 for write
address boundaries and Section 2.6.4 read address boundaries.
2.5
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table 2-2 shows the
method of forwarding used for each type of write operation.
Table 2-2. Write Transaction Forwarding
Type of Transaction
Type of Forwarding
Memory Write
Posted (except VGA memory)
Memory Write and Invalidate
Posted
Memory Write to VGA memory
Delayed
I/O Write
Delayed
Type 1 Configuration Write
Delayed
07-0067
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