參數資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數： | 61/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標準包裝： | 39 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應商設備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 64 of 82
March 20, 2007 – Revision 1.01
Bit
Function
Type
Description
15:12
I/O Limit
Address
[15:12]
RW
Defines the top address of the I/O address range for the bridge to determine when
to forward I/O transactions from one interface to the other. The upper 4 bits
correspond to address bits [15:12] and are writable. The lower 12 bits
corresponding to address bits [11:0] are assumed to be FFFh. The upper 16 bits
corresponding to address bits [31:16] are defined in the I/O limit address upper 16
bits address register
Reset to 0
13.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
20:16
Reserved
RO
Reset to 0
21
66MHz
Capable
RO
Set to 1 to indicate bridge is capable of 66MHz operation on the secondary
interface
Reset to 1
22
Reserved
RO
Reset to 0
23
Fast Back-to-
Back Capable
RO
Set to 1 to indicate bridge is capable of decoding fast back-to-back transactions
on the secondary interface to different targets
Reset to 1
24
Data Parity
Error Detected
RWC
Set to 1 when S_PERR# is asserted and bit 6 of command register is set
Reset to 0
26:25
DEVSEL_L
timing
RO
DEVSEL# timing (medium decoding)
01: medium DEVSEL# decoding
Reset to 01
27
Signaled Target
Abort
RWC
Set to 1 (by a target device) whenever a target abort cycle occurs on its secondary
interface
Reset to 0
28
Received
Target Abort
RWC
Set to 1 (by a master device) whenever transactions on its secondary interface are
terminated with target abort
Reset to 0
29
Received
Master Abort
RWC
Set to 1 (by a master) when transactions on its secondary interface are terminated
with Master Abort
Reset to 0
30
Received
System Error
RWC
Set to 1 when S_SERR# is asserted
Reset to 0
31
Detected Parity
Error
RWC
Set to 1 when address or data parity error is detected on the secondary interface
Reset to 0
13.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h
Bit
Function
Type
Description
3:0
Reserved
RO
Reset to 0
07-0067
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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