參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 10/82頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 18 of 82
March 20, 2007 – Revision 1.01
2.5.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate” transactions.
When the bridge determines that a memory write transaction is to be forwarded across the bridge, the
bridge asserts DEVSEL# with medium timing and TRDY# in the next cycle, provided that enough
buffer space is available in the posted memory write queue for the address and at least one DWORD of
data. Under this condition, the bridge accepts write data without obtaining access to the target bus. The
bridge can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is
inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the
target. The bridge continues to accept write data until one of the following events occurs:
The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB
boundary, depending on the transaction type.
The posted write data buffer fills up.
When one of the last two events occurs, the bridge returns a target disconnect to the requesting initiator
on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, the bridge asserts its request on
the target bus. This can occur while the bridge is still receiving data on the initiator bus. When the
grant for the target bus is received and the target bus is detected in the idle condition, the bridge asserts
FRAME# and drives the stored write address out on the target bus. On the following cycle, the bridge
drives the first DWORD of write data and continues to transfer write data until all write data
corresponding to that transaction is delivered, or until a target termination is received. As long as write
data exists in the queue, the bridge can drive one DWORD of write data each PCI clock cycle; that is,
no master wait states are inserted. If write data is flowing through the bridge and the initiator stalls, the
bridge will signal the last data phase for the current transaction at the target bus if the queue empties.
The bridge will restart the follow-on transactions if the queue has new data.
The bridge ends the transaction on the target bus when one of the following conditions is met:
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (the bridge starts another transaction to deliver
the rest of the write data).
The target returns a target abort (the bridge discards remaining write data).
The master latency timer expires, and the bridge no longer has the target bus grant (the bridge starts
another transaction to deliver remaining write data).
Section 2.8.3.2 provides detailed information about how the bridge responds to target termination
during posted write transactions.
2.5.2
MEMORY WRITE AND INVALIDATE
Posted write forwarding is used for Memory Write and Invalidate transactions.
If offset 74h bits [8:7] = 11, the bridge disconnects Memory Write and Invalidate commands at aligned
cache line boundaries. The cache line size value in the cache line size register gives the number of
DWORD in a cache line.
07-0067
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