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參數(shù)資料
| 型號(hào)： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 13/82頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 20 of 82
March 20, 2007 – Revision 1.01
discards the delayed write completion from the delayed transaction completion queue. The bridge also
conditionally asserts P_SERR# (see Section 5.4).
2.5.4
WRITE TRANSACTION BOUNDARIES
The bridge imposes internal address boundaries when accepting write data. The aligned address
boundaries are used to prevent the bridge from continuing a transaction over a device address boundary
and to provide an upper limit on maximum latency. The bridge returns a target disconnect to the
initiator when it reaches the aligned address boundaries under conditions shown in Table 2-3.
Table 2-3. Write Transaction Disconnect Address Boundaries
Type of Transaction
Condition
Aligned Address Boundary
Delayed Write
All
Disconnects after one data transfer
Posted Memory Write
Memory write disconnect control bit = 0
(1)
4KB aligned address boundary
Posted Memory Write
Memory write disconnect control bit = 1
(1)
Disconnects at cache line boundary
Posted Memory Write and
Invalidate
Cache line size
≠ 1, 2, 4, 8, 16
4KB aligned address boundary
Posted Memory Write and
Invalidate
Cache line size = 1, 2, 4, 8, 16
Cache line boundary if posted memory
write data FIFO does not have enough
space for the cache line
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 44h in the configuration space.
2.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
The bridge continues to accept posted memory write transactions as long as space for at least one
DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the
initiator terminates the write transaction, the bridge returns a target disconnect to the initiator.
Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue
exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same
time. See Chapter 5 for information about how multiple posted and delayed write transactions are
ordered.
2.5.6
FAST BACK-TO-BACK TRANSACTIONS
The bridge can recognize and post fast back-to-back write transactions. When the bridge cannot accept
the second transaction because of buffer space limitations, it returns a target retry to the initiator. The
fast back-to-back enable bit must be set in the command register for upstream write transactions, and in
the bridge control register for downstream write transactions.
2.6
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing the bridge. Delayed read transactions
are treated as either prefetchable or non-prefetchable. Table 2-5 shows the read behavior, prefetchable
or non-prefetchable, for each type of read operation.
07-0067
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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