The bridge incorporates functionality that m" />
參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 49/82頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 53 of 82
March 20, 2007 – Revision 1.01
9
PCI POWER MANAGEMENT
The bridge incorporates functionality that meets the requirements of the PCI Power Management
Specification, Revision 1.1. These features include:
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address mechanism
Support for D0, D3hot, and D3cold power management states
Support for D0, D1, D2, D3hot , and D3cold power management states for devices behind the bridge
Support of the B2 secondary bus power state when in the D3hot power management state
Table 9-1 shows the states and related actions that the bridge performs during power management
transitions. (No other transactions are permitted.)
Table 9-1. Power Management Transitions
Current Status
Next State
Action
D0
D3cold
Power has been removed from bridge. A power-up reset must be performed to
bring bridge to D0.
D0
D3hot
If enabled to do so by the BPCCE pin, bridge will disable the secondary clocks
and drive them LOW.
D0
D2
Unimplemented power state. bridge will ignore the write to the power state
bits (power state remains at D0).
D0
D1
Unimplemented power state. bridge will ignore the write to the power state
bits (power state remains at D0).
D3hot
D0
Bridge enables secondary clock outputs and performs an internal chip reset.
Signal S_RST# will not be asserted. All registers will be returned to the reset
values and buffers will be cleared.
D3hot
D3cold
Power has been removed from bridge. A power-up reset must be performed to
bring bridge to D0.
D3cold
D0
Power-up reset. Bridge performs the standard power-up reset functions as
described in Section 10.
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do not
pass through PCI-to-PCI bridges.
10
RESET
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
10.1 PRIMARY INTERFACE RESET
The bridge has a reset input, P_RST#. When P_RST# is asserted, the following events occur:
Bridge immediately tri-states all primary and secondary PCI interface signals.
Bridge performs a chip reset.
Registers that have default values are reset.
P_RST# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLKOUT. The bridge
is not accessible during P_RST#. After P_RST# is de-asserted, the bridge remains inaccessible for 16
PCI clocks before the first configuration transaction can be accepted.
07-0067
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