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參數(shù)資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 38/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 43 of 82
March 20, 2007 – Revision 1.01
Bridge completes the transaction normally.
For upstream transactions, when the bridge detects a read data parity error on the primary bus, the
following events occur:
Bridge asserts P_PERR# two cycles following the data transfer, if the primary interface parity error
response bit is set in the command register.
Bridge sets the detected parity error bit in the primary status register.
Bridge sets the data parity detected bit in the primary status register, if the primary interface parity-
error-response bit is set in the command register.
Bridge forwards the bad parity with the data back to the initiator on the secondary bus. If the data
with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is
discarded and the data with bad parity is not returned to the initiator.
Bridge completes the transaction normally.
The bridge returns to the initiator the data and parity that was received from the target. When the
initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR#
two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling
a parity error condition; therefore, when the bridge detects PERR# asserted while returning read data to
the initiator, the bridge does not take any further action and completes the transaction normally.
5.2.3
DELAYED WRITE TRANSACTIONS
When the bridge detects a data parity error during a delayed write transaction, the initiator drives data
and data parity, and the target checks parity and conditionally asserts PERR#.
For delayed write transactions, a parity error can occur at the following times:
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When the bridge completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address parity, data, byte
enable bits, and data parity are all captured and a target retry is returned to the initiator. When the
bridge detects a parity error on the write data for the initial delayed write request transaction, the
following events occur:
If the parity-error-response bit corresponding to the initiator bus is set, the bridge asserts TRDY# to
the initiator and the transaction is not queued. If multiple data phases are requested, STOP# is also
asserted to cause a target disconnect. Two cycles after the data transfer, the bridge also asserts
PERR#.
If the parity-error-response bit is not set, the bridge returns a target retry. It queues the transaction
as usual. The bridge does not assert PERR#. In this case, the initiator repeats the transaction.
The bridge sets the detected-parity-error bit in the status register corresponding to the initiator bus,
regardless of the state of the parity-error-response bit.
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent
delayed write transactions on the initiator bus, it is possible that the initiator’s re-attempts of the write
transaction may not match the original queued delayed write information contained in the delayed
transaction queue. In this case, a master timeout condition may occur, possibly resulting in a system
error (P_SERR# assertion).
07-0067
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8148ANBE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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