參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 22/82頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 29 of 82
March 20, 2007 – Revision 1.01
If the bridge is pre-fetching read data when it terminates the transaction because the master latency
timer expires, it does not repeat the transaction to obtain more data.
2.8.2
MASTER ABORT RECEIVED BY PI7C8140A
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by the
target within five clock cycles of the assertion of FRAME#, the bridge terminates the transaction with a
master abort. This sets the received-master-abort bit in the status register corresponding to the target
bus.
For delayed read and write transactions, the bridge is able to reflect the master abort condition back to
the initiator. When the bridge detects a master abort in response to a delayed transaction, and when the
initiator repeats the transaction, the bridge does not respond to the transaction with DEVSEL#, which
induces the master abort condition back to the initiator. The transaction is then removed from the
delayed transaction queue. When a master abort is received in response to a posted write transaction,
the bridge discards the posted write data and makes no more attempts to deliver the data. The bridge
sets the received-master-abort bit in the status register when the master abort is received on the primary
bus, or it sets the received master abort bit in the secondary status register when the master abort is
received on the secondary interface. When master abort is detected in posted write transaction with both
master-abort-mode bit (bit 5 of bridge control register) and the SERR# enable bit (bit 8 of command
register for secondary bus) are set, the bridge asserts P_SERR# if the master-abort-on-posted-write is
not set. The master-abort-on-posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h).
Note: When the bridge performs a Type 1 to special cycle conversion, a master abort is the expected
termination for the special cycle on the target bus. In this case, the master abort received bit is not set,
and the Type 1 configuration transaction is disconnected after the first data phase.
2.8.3
TARGET TERMINATION RECEIVED BY PI7C8140A
When the bridge initiates a transaction on the target bus and the target responds with DEVSEL#, the
target can end the transaction with one of the following types of termination:
Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
The bridge handles these terminations in different ways, depending on the type of transaction being
performed.
2.8.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE
When the bridge initiates a delayed write transaction, the type of target termination received from the
target can be passed back to the initiator. Table 2-7 shows the response to each type of target
termination that occurs during a delayed write transaction.
The bridge repeats a delayed write transaction until one of the following conditions is met:
07-0067
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