參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 66/82頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 69 of 82
March 20, 2007 – Revision 1.01
Bit
Function
Type
Description
1
Memory Write
Disconnect
Control
RW
Controls when the bridge (as a target) disconnects memory write transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
3:2
Reserved
RO
Reserved. Returns 0 when read. Reset to 0.
4
Secondary Bus
Prefetch
Disable
RW
Controls the bridge’s ability to prefetch during upstream memory read
transactions
0: Bridge prefetches and does not forward byte enable bits during upstream
memory read transactions.
1: Bridge requests only 1 DWORD from the target and forwards read byte enable
bits during upstream memory reads.
Reset to 0
7:5
Reserved
RO
Reserved. Returns 0 when read. Reset to 0
8
Chip Reset
RWR
Controls the chip and secondary bus reset.
0: Bridge is ready for operation
1: Causes bridge to perform a chip reset. Data buffers, configuration registers, and
both primary and secondary are reset to their initial states. Bridge clears this bit
once chip reset is complete. Bridge can then be reconfigured.
9
Test Mode 1
RW
Controls the ability to test bridge’s behavior
0: minimum of 8 free space in data FIFO to accept memory burst writes
1: minimum of 1 free space in data FIFO to accept memory burst writes
Reset to 0
11:10
Test Mode 2
RW
Controls the ability to test bridge’s behavior
00: enable out of order transactions between all 4 DTR requests
01: accept 3 DTR requests at a time and they may be out of order
10: only the 2 DTR requests at the top of the 2 FIFO’s may be out of order
11: no out of order transactions supported between DTR requests
Reset to 00
12
Test Mode 3
RW
Controls the ability to test bridge’s behavior
0: 4 memory write transactions can be accepted at a time
1: 2 memory write transactions can be accepted at a time
Reset to 0
15:13
Reserved
RO
Reserved. Returns 000 when read. Reset to 000.
07-0067
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